/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/* Copyright (c) 2023 Graphcore Ltd. */
/*
 * Automatically generated file.
 *
 * IPU architecture map.
 */

#ifndef _ipu_arch_map_h_
#define _ipu_arch_map_h_

#include <linux/types.h>

#define IAI_IPU0_SUPPORTED
#define IPU0_ARCH_MAP_INDEX (0)
#define IAI_IPU1_SUPPORTED
#define IPU1_ARCH_MAP_INDEX (0)
#define IAI_IPU2_SUPPORTED
#define IPU2_ARCH_MAP_INDEX (1)
#define IAI_IPU21_SUPPORTED
#define IPU21_ARCH_MAP_INDEX (2)
#define IAI_IPU30_SUPPORTED
#define IPU30_ARCH_MAP_INDEX (3)

#define NUM_NLCS    (10)

struct ipu_arch_map {
	u32 IPU_TILE_INSTANCES_WITH_REPAIR;
	u32 NLC_CSR_CORERRCNT_MASK;
	u32 NLC_CSR_CORERRCNT_SHIFT;
	u32 NLC_CSR_CORERROR_MASK;
	u32 NLC_CSR_CORERROR_SHIFT;
	u32 NLC_CSR_IPUID_MASK;
	u32 NLC_CSR_IPUID_SHIFT;
	u32 NLC_CSR_OFFSET;
	u32 NLC_LCSR_COREDN_MASK;
	u32 NLC_LCSR_COREDN_SHIFT;
	u32 NLC_LCSR_LINKDN_MASK;
	u32 NLC_LCSR_LINKDN_SHIFT;
	u32 NLC_LCSR_OFFSET;
	u32 PCI_COMPLEX_CCSR_DUALPCI_MASK;
	u32 PCI_COMPLEX_CCSR_DUALPCI_SHIFT;
	u32 PCI_COMPLEX_CCSR_HUGEPAGE_MASK;
	u32 PCI_COMPLEX_CCSR_HUGEPAGE_SHIFT;
	u32 PCI_COMPLEX_CCSR_OFFSET;
	u32 PCI_COMPLEX_CIUERRVR_IPUSOFTERR_MASK;
	u32 PCI_COMPLEX_CIUERRVR_IPUSOFTERR_SHIFT;
	u32 PCI_COMPLEX_CIUERRVR_OFFSET;
	u32 PCI_COMPLEX_EXCHWINDOWBASER_HEXOPT_MASK;
	u32 PCI_COMPLEX_EXCHWINDOWBASER_HEXOPT_SHIFT;
	u32 PCI_COMPLEX_EXCHWINDOWBASER_OFFSET;
	u32 PCI_COMPLEX_HEXOPTUPDDATAHIR_OFFSET;
	u32 PCI_COMPLEX_HEXOPTUPDDATALOR_OFFSET;
	u32 PCI_COMPLEX_HEXOPTUPDINDEXR_OFFSET;
	u32 PCI_COMPLEX_HSPGS1CR_MARK_MASK;
	u32 PCI_COMPLEX_HSPGS1CR_MARK_SHIFT;
	u32 PCI_COMPLEX_HSPGS1CR_NOTIFY_MASK;
	u32 PCI_COMPLEX_HSPGS1CR_NOTIFY_SHIFT;
	u32 PCI_COMPLEX_HSPGS1CR_OFFSET;
	u32 PCI_COMPLEX_HSPGS1HILR_OFFSET;
	u32 PCI_COMPLEX_HSPGS1LR_OFFSET;
	u32 PCI_COMPLEX_HSPGS2CR_MARK_MASK;
	u32 PCI_COMPLEX_HSPGS2CR_MARK_SHIFT;
	u32 PCI_COMPLEX_HSPGS2CR_NOTIFY_MASK;
	u32 PCI_COMPLEX_HSPGS2CR_NOTIFY_SHIFT;
	u32 PCI_COMPLEX_HSPGS2CR_OFFSET;
	u32 PCI_COMPLEX_HSPGS2HILR_OFFSET;
	u32 PCI_COMPLEX_HSPGS2LR_OFFSET;
	u32 PCI_COMPLEX_MCUCMDR_OFFSET;
	u32 PCI_COMPLEX_MCUDATR0_OFFSET;
	u32 PCI_COMPLEX_MCUDATR1_OFFSET;
	u32 PCI_COMPLEX_MCUDATR2_OFFSET;
	u32 PCI_COMPLEX_MCUDATR3_OFFSET;
	u32 PCI_COMPLEX_PCICMDR_OFFSET;
	u32 PCI_COMPLEX_PCIDATR0_OFFSET;
	u32 PCI_COMPLEX_PCIDATR1_OFFSET;
	u32 PCI_COMPLEX_PCIDATR2_OFFSET;
	u32 PCI_COMPLEX_PCIDATR3_OFFSET;
	u32 PCI_COMPLEX_TILEUPDR_OFFSET;
	u32 SOC_CBUS0_BASE;
	u32 SOC_IPU_MEM_BASE;
	u32 SOC_IPU_MEM_TILE_STRIDE;
	u32 SOC_NLC_E_2A_BASE;
	u32 SOC_NLC_E_2B_BASE;
	u32 SOC_NLC_E_2C_BASE;
	u32 SOC_NLC_E_3A_BASE;
	u32 SOC_NLC_E_3B_BASE;
	u32 SOC_NLC_E_3C_BASE;
	u32 SOC_NLC_W_0B_BASE;
	u32 SOC_NLC_W_0C_BASE;
	u32 SOC_NLC_W_1B_BASE;
	u32 SOC_NLC_W_1C_BASE;
	u32 SS_IPUCLKCOUNTLSBR_OFFSET;
	u32 SS_SIPUPLLCR_IPUCLKCNTEN_MASK;
	u32 SS_SIPUPLLCR_IPUCLKCNTEN_SHIFT;
	u32 SS_SIPUPLLCR_OFFSET;
	u32 TDBG_TDI_REGISTER_WIDTH;
	u32 TDI_CTXT_STS_MERR_MASK;
	u32 TDI_CTXT_STS_MERR_SHIFT;
	u32 TDI_CTXT_STS_OFFSET;
};

extern struct ipu_arch_map ipu_arch_maps[4];

#endif