/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/* Copyright (c) 2015-2022 Graphcore Ltd. */
/*
 * IPU device driver.
 *
 * Description: IPU defines.
 */

#ifndef _ipu_defines_h_
#define _ipu_defines_h_

#include <linux/types.h>

#define IPU0_PCI_SUBSYSTEM_ID (0x0000)
#define IPU1_PCI_SUBSYSTEM_ID (0x0001)
#define IPU2_PCI_SUBSYSTEM_ID (0x0002)
#define IPU2_1_PCI_SUBSYSTEM_ID (0x0102)
#define IPU2_1_2_PCI_SUBSYSTEM_ID (0x1102)

// Graphcore vendor id
#define IPU_PCI_VENDOR_ID (0x1d95)
// IPU1 card device ids
#define IPU_PCI_DEVICE_ID_C2 (0x0001)
#define IPU_PCI_DEVICE_ID_S1 (0x0002)
// IPU2 card device ids
#define IPU_PCI_DEVICE_ID_C200    (0x0003)
#define IPU_PCI_DEVICE_ID_M2000   (0x2000)
#define IPU_PCI_DEVICE_ID_M2000W  (0x2001)
// IPU21 card device ids
#define IPU_PCI_DEVICE_ID_C600    (0x0600)

#define PCI_DEVICE_ID_INVALID (-1)

// Device File descriptors
#define PCI_CONFIG_BAR_SIZE (0x80000)
#define PCI_EXCHANGE_BAR_SIZE_IPU1 (0x20000000)
#define PCI_EXCHANGE_BAR_START_OFFSET_IPU1 (0xC000000)
#define PCI_EXCHANGE_BAR_SIZE_IPU2 (0x4000000)

/* MCU has two groups of events - error events and non-error events.
 * Both non-error and error events are placed in the event buffer.
 *
 * The last non-error event of each type is interrogable via sysfs
 * last_icu_events directory.  MCU_NUM_EVENT_TYPES is the upper limit of these
 * non-error event types exposed by sysfs.
 */
#define MCU_NUM_EVENT_TYPES (32)

/* Mailbox size in u32 words (including the MDR header)*/
#define MBOX_MSG_SIZE_WORDS (5)

/* An unused magic number from Documentation/ioctl/ioctl-number.txt. */
#define IPU_IOCTL_MAGIC_VAL (0xed)

/* Ipu IOCTL commands. */
enum ipu_ioctls {
	IPU_USER_ATTACH = _IOWR(IPU_IOCTL_MAGIC_VAL, 10, unsigned long),
	IPU_BUFFER_ATTACH = _IOWR(IPU_IOCTL_MAGIC_VAL, 11, unsigned long),
	IPU_BUFFER_DETACH = _IOWR(IPU_IOCTL_MAGIC_VAL, 12, unsigned long),
	IPU_SELECT_BAR = _IOWR(IPU_IOCTL_MAGIC_VAL, 13, unsigned long),
	IPU_SET_IPU_ID = _IOWR(IPU_IOCTL_MAGIC_VAL, 14, unsigned long),
	IPU_GET_DRIVER_VERSION = _IOR(IPU_IOCTL_MAGIC_VAL, 15, unsigned int),
	IPU_RESTORE_BOARD_INFO = _IO(IPU_IOCTL_MAGIC_VAL, 16),
	IPU_SET_PARITY_INIT_FLAG = _IOW(IPU_IOCTL_MAGIC_VAL, 17, unsigned int),
	IPU_BUFFER_DETACH_ALL = _IO(IPU_IOCTL_MAGIC_VAL, 18),
	IPU_GET_CONTIGUOUS_BUFFER = _IOWR(IPU_IOCTL_MAGIC_VAL, 19,
					  unsigned long),
	IPU_STORE_SENSOR_READING = _IOW(IPU_IOCTL_MAGIC_VAL, 20,
					unsigned long),
	IPU_PUT_ALL_CONTIGUOUS_BUFFER = _IOWR(IPU_IOCTL_MAGIC_VAL, 21,
					      unsigned long),
	IPU_MASK_INTERRUPT = _IOWR(IPU_IOCTL_MAGIC_VAL, 22, unsigned long),
	IPU_UNMASK_INTERRUPT = _IOWR(IPU_IOCTL_MAGIC_VAL, 23, unsigned long),
	IPU_GET_CONTIGUOUS_BUFFER_ENTRY = _IOWR(IPU_IOCTL_MAGIC_VAL, 24,
						uint64_t),
	IPU_READ_CONTIGUOUS_BUFFER = _IOWR(IPU_IOCTL_MAGIC_VAL, 25,
					   uint64_t),
	IPU_WRITE_CONTIGUOUS_BUFFER = _IOWR(IPU_IOCTL_MAGIC_VAL, 26,
					    uint64_t),
	IPU_PUT_CONTIGUOUS_BUFFER = _IOWR(IPU_IOCTL_MAGIC_VAL, 27,
					  uint64_t),
	IPU_PUT_HSPGS_NOTIFY_ADDR = _IOWR(IPU_IOCTL_MAGIC_VAL, 28,
					  uint64_t),
	IPU_MAILBOX_READ_ONLY = _IOR(IPU_IOCTL_MAGIC_VAL, 29, unsigned long),
	IPU_MAILBOX_WRITE_ONLY = _IOW(IPU_IOCTL_MAGIC_VAL, 30, unsigned long),
	IPU_MAILBOX_WRITE_READ = _IOWR(IPU_IOCTL_MAGIC_VAL, 31, unsigned long),
	IPU_MAILBOX_GET_OFFSETS = _IOR(IPU_IOCTL_MAGIC_VAL, 32, unsigned long),
	IPU_MCU_GET_EVENT = _IOR(IPU_IOCTL_MAGIC_VAL, 33, unsigned long),
	IPU_STOP_MONITORING_THREADS = _IO(IPU_IOCTL_MAGIC_VAL, 34),
	IPU_START_MONITORING_THREADS = _IO(IPU_IOCTL_MAGIC_VAL, 35),
	IPU_ACCUMULATE_NLC_ERRCNT = _IO(IPU_IOCTL_MAGIC_VAL, 36),
	IPU_READ_AER_DATA = _IO(IPU_IOCTL_MAGIC_VAL, 37),
	IPU_ENABLE_GWLINKS = _IOW(IPU_IOCTL_MAGIC_VAL, 38, unsigned int),
	IPU_SET_THROTTLE_LOG_THRESHOLDS = _IOW(IPU_IOCTL_MAGIC_VAL, 39,
					       unsigned int),
	IPU_CLEAR_SPB_SERVICE_TABLES = _IO(IPU_IOCTL_MAGIC_VAL, 40),
	IPU_SET_USER_DATA = _IOW(IPU_IOCTL_MAGIC_VAL, 41, unsigned int),
	IPU_GET_USER_DATA = _IOR(IPU_IOCTL_MAGIC_VAL, 42, unsigned long),
	IPU_SET_SPB_MULTI_READ_ST_ENABLE = _IOW(IPU_IOCTL_MAGIC_VAL, 43,
						unsigned int),
	IPU_SET_HEXOPT_IDENTITY_TABLE = _IO(IPU_IOCTL_MAGIC_VAL, 44),
	IPU_RESET = _IOW(IPU_IOCTL_MAGIC_VAL, 45, unsigned int),
	IPU_SECONDARY_CONFIG_OPS = _IOW(IPU_IOCTL_MAGIC_VAL, 46, unsigned long),
	IPU_SET_SECONDARY_IPUID = _IOW(IPU_IOCTL_MAGIC_VAL, 47, unsigned long),
};

/* Keep old ioctl names for backwards compatibility. */
#define IPU_STOP_TILE_CLK_THREAD  IPU_STOP_MONITORING_THREADS
#define IPU_START_TILE_CLK_THREAD IPU_START_MONITORING_THREADS

struct mailbox_msg {
	unsigned int msg[MBOX_MSG_SIZE_WORDS];
};

struct mailbox_arg {
	const void *sent_msg;
	void *recv_msg;
};

struct hspgs_notify_addr {
	unsigned long hsp[2];
};

struct ipu_sensor_reading_t {
	unsigned int sensor_type;
	unsigned int index;
	int value;
};

struct contiguous_buffer_ops_t {
	unsigned long handle;
	unsigned long offset;
	unsigned long user_buffer;
	unsigned long size;
};

struct contiguous_buffer_info_t {
	uintptr_t start; /* Base address of reserved memory */
	unsigned long size;
};

struct secondary_config_reg_ops {
	__UINT32_TYPE__ offset;
	__UINT32_TYPE__ value;
	__UINT32_TYPE__ read;
	__UINT32_TYPE__ write;
};

struct throttle_log_thresholds_t {
	unsigned long level1;
	unsigned long level2;
	unsigned long level3;
};

/* IPU interrupt numbers, must match GCDA types */
enum ipu_isr {
	IPU_IPUEX_ISR = 0,
	IPU_ICU_ISR,
	IPU_HSPGS1E0_ISR,
	IPU_HSPGS1E1_ISR,
	IPU_HSPGS2E0_ISR,
	IPU_HSPGS2E1_ISR,
	IPU_ICU_MSG_ISR,
	IPU_RESERVED2_ISR,
	IPU_NUM_INTERRUPTS
};

#define IPU_ALL_INTERRUPTS (0xFF)

static inline int ipu_arch_num_from_subsystem(unsigned int subsystem_id)
{
	switch (subsystem_id) {
	case IPU0_PCI_SUBSYSTEM_ID:
		return 0;
	case IPU1_PCI_SUBSYSTEM_ID:
		return 1;
	case IPU2_PCI_SUBSYSTEM_ID:
		return 2;
	case IPU2_1_PCI_SUBSYSTEM_ID:
		return 21;
	default:
		return -1;
	}
}

#endif