2026-09-11T17:16:38.816326Z  INFO compiling kernel source=artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S name="static_runtime" target=ipu21
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 0
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:87:1: note: while in macro instantiation
GELU_FP8_QUAD 0, 0
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 0
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:87:1: note: while in macro instantiation
GELU_FP8_QUAD 0, 0
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 2
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:88:1: note: while in macro instantiation
GELU_FP8_QUAD 2, 1
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 2
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:88:1: note: while in macro instantiation
GELU_FP8_QUAD 2, 1
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 4
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:89:1: note: while in macro instantiation
GELU_FP8_QUAD 4, 2
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 4
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:89:1: note: while in macro instantiation
GELU_FP8_QUAD 4, 2
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 6
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:90:1: note: while in macro instantiation
GELU_FP8_QUAD 6, 3
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 6
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:90:1: note: while in macro instantiation
GELU_FP8_QUAD 6, 3
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 8
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:91:1: note: while in macro instantiation
GELU_FP8_QUAD 8, 4
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 8
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:91:1: note: while in macro instantiation
GELU_FP8_QUAD 8, 4
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 10
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:92:1: note: while in macro instantiation
GELU_FP8_QUAD 10, 5
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 10
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:92:1: note: while in macro instantiation
GELU_FP8_QUAD 10, 5
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 12
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:93:1: note: while in macro instantiation
GELU_FP8_QUAD 12, 6
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 12
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:93:1: note: while in macro instantiation
GELU_FP8_QUAD 12, 6
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 14
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:94:1: note: while in macro instantiation
GELU_FP8_QUAD 14, 7
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 14
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:94:1: note: while in macro instantiation
GELU_FP8_QUAD 14, 7
^
<instantiation>:9:29: error: invalid operand for instruction
 f16v4min $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 0
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:102:1: note: while in macro instantiation
GELU_FP8_QUAD 0, 0
^
<instantiation>:11:29: error: invalid operand for instruction
 f16v4max $a0:1, $a0:1, $a2:BL
                            ^
<instantiation>:3:1: note: while in macro instantiation
GELU_TWO_PAIRS 0
^
/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S:102:1: note: while in macro instantiation
GELU_FP8_QUAD 0, 0
^
Error: Assembler failed to run for input:<
.# 1 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
# 1 "<built-in>" 1
# 1 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S" 2
# 1 "/srv/home/gc-sdk/ipu-stack/device/static_runtime.S" 1
# 1 "/srv/home/gc-sdk/poplar_sdk-ubuntu_20_04-3.4.0+1507-69d9d03fd8/poplar-ubuntu_20_04-3.4.0+73-aa67dd6164/lib/graphcore/include/arch/gc_tile_defines.h" 1 3
# 21 "/srv/home/gc-sdk/poplar_sdk-ubuntu_20_04-3.4.0+1507-69d9d03fd8/poplar-ubuntu_20_04-3.4.0+73-aa67dd6164/lib/graphcore/include/arch/gc_tile_defines.h" 3
# 1 "/srv/home/gc-sdk/poplar_sdk-ubuntu_20_04-3.4.0+1507-69d9d03fd8/poplar-ubuntu_20_04-3.4.0+73-aa67dd6164/lib/graphcore/include/arch/gc_tilearch_ipu21.h" 1 3
# 22 "/srv/home/gc-sdk/poplar_sdk-ubuntu_20_04-3.4.0+1507-69d9d03fd8/poplar-ubuntu_20_04-3.4.0+73-aa67dd6164/lib/graphcore/include/arch/gc_tile_defines.h" 2 3
# 1 "/srv/home/gc-sdk/poplar_sdk-ubuntu_20_04-3.4.0+1507-69d9d03fd8/poplar-ubuntu_20_04-3.4.0+73-aa67dd6164/lib/graphcore/include/arch/gc_tileimplconsts_ipu21.h" 1 3
# 23 "/srv/home/gc-sdk/poplar_sdk-ubuntu_20_04-3.4.0+1507-69d9d03fd8/poplar-ubuntu_20_04-3.4.0+73-aa67dd6164/lib/graphcore/include/arch/gc_tile_defines.h" 2 3
# 2 "/srv/home/gc-sdk/ipu-stack/device/static_runtime.S" 2

 .text
 .allow_optimizations

 .set TILE_MUX_HOST, 0x600
 .set TILE_MUX_EXCHANGE, 0x640
 .set WORKER_BASE_STRIDE, 0x100
 .set HOST_RUN_DESCRIPTOR_BYTES, 3 * 4
 .set HOST_PACKET_ADDRESS, 0x50000
 .set SYNC_ALL, 7
 .set SYNC_COMPUTE_SET, (2)
 .set SYNC_SUPERVISOR, 3
 .set OPCODE_SYNC, 0x41800000
 .set PRNG_WARMUP_REPEAT_COUNT, 15

 .extern ipu_stack_static_worker_sync_context
 .extern ipu_stack_static_worker_stack_base
 .extern ipu_stack_static_prng_seed
 .extern ipu_stack_static_program
 .extern ipu_stack_static_host_staging
 .extern ipu_stack_static_completion

 .section .text.ipu_stack_static_start,"ax",@progbits
 .globl ipu_stack_static_start
 .p2align 2
 nop
 .type ipu_stack_static_start,@function
ipu_stack_static_start:
 .supervisor
 .long OPCODE_SYNC | SYNC_SUPERVISOR

 .long OPCODE_SYNC | SYNC_COMPUTE_SET
 setzi $m0, TILE_MUX_EXCHANGE
 put 0xa0, $m0
 put 0xa7, $m15


 get $m0, $FP_ICTL
 setzi $m1, 1 << (2)
 or $m0, $m0, $m1
 put $FP_ICTL, $m0
 setzi $m11, ipu_stack_static_worker_stack_base
 put 0x21, $m11
 add $m11, $m11, WORKER_BASE_STRIDE
 put 0x22, $m11
 add $m11, $m11, WORKER_BASE_STRIDE
 put 0x23, $m11
 add $m11, $m11, WORKER_BASE_STRIDE
 put 0x24, $m11
 add $m11, $m11, WORKER_BASE_STRIDE
 put 0x25, $m11
 add $m11, $m11, WORKER_BASE_STRIDE
 put 0x26, $m11
 add $m11, $m11, WORKER_BASE_STRIDE
 setzi $m0, ipu_stack_static_worker_init
 runall $m0, $m15, 0
 .long OPCODE_SYNC | SYNC_COMPUTE_SET
 setzi $m0, TILE_MUX_HOST
 put 0xa0, $m0
 .long OPCODE_SYNC | SYNC_ALL
 setzi $m0, TILE_MUX_EXCHANGE
 put 0xa0, $m0
 setzi $m0, ipu_stack_static_program
 br $m0
 .size ipu_stack_static_start, .-ipu_stack_static_start

 .section .text.ipu_stack_static_worker_init,"ax",@progbits
 .globl ipu_stack_static_worker_init
 .p2align 2
 .type ipu_stack_static_worker_init,@function
ipu_stack_static_worker_init:
 .worker
 setzi $m0, ipu_stack_static_worker_sync_context
 get $m1, 1
 and $m1, $m1, 7
 or $m0, $m0, $m1
 st32 $m0, $m12, $m15, 0
 ld32 $a0, $m12, $m15, 0
 put 0x7, $a0
 setzi $m0, ipu_stack_static_prng_seed
 or $m0, $m0, $m1
 st32 $m0, $m12, $m15, 0
 ld32 $a0, $m12, $m15, 0
 uput $PRNG_SEED, $a0
 { rpt PRNG_WARMUP_REPEAT_COUNT, 0
   fnop }
 { nop
   urand64 $azeros }
 exitz $m15
 .size ipu_stack_static_worker_init, .-ipu_stack_static_worker_init

 .section .text.ipu_stack_static_worker_barrier,"ax",@progbits
 .globl ipu_stack_static_worker_barrier
 .p2align 2
 .type ipu_stack_static_worker_barrier,@function
ipu_stack_static_worker_barrier:
 .supervisor
 setzi $m0, ipu_stack_static_worker_barrier_worker
 runall $m0, $m15, 0
 .long OPCODE_SYNC | SYNC_COMPUTE_SET
 br $m7
 .size ipu_stack_static_worker_barrier, .-ipu_stack_static_worker_barrier

 .section .text.ipu_stack_static_worker_barrier_worker,"ax",@progbits
 .p2align 2
 .type ipu_stack_static_worker_barrier_worker,@function
ipu_stack_static_worker_barrier_worker:
 .worker
 exitz $m15
 .size ipu_stack_static_worker_barrier_worker, .-ipu_stack_static_worker_barrier_worker

 .section .text.static_copy_u32,"ax",@progbits

 .globl static_copy_u32
 .p2align 2
 .type static_copy_u32,@function
static_copy_u32:
 .supervisor
 brz $m4, .Lcopy_u32_done
.Lcopy_u32:
 ld32 $m0, $m3, $m15, 0
 st32 $m0, $m2, $m15, 0
 add $m3, $m3, 4
 add $m2, $m2, 4
 sub $m4, $m4, 1
 brnz $m4, .Lcopy_u32
.Lcopy_u32_done:
 br $m10
 .size static_copy_u32, .-static_copy_u32

 .section .text.static_copy_u16,"ax",@progbits


 .globl static_copy_u16
 .p2align 2
 .type static_copy_u16,@function
static_copy_u16:
 .supervisor
 brz $m4, .Lcopy_u16_done
.Lcopy_u16:
 ld32 $m3, $m10, $m15, 0
 ld32 $m2, $m10, $m15, 1
 add $m10, $m10, 8
 mov $m6, $m3
 shr $m6, $m6, 2
 shl $m6, $m6, 2
 ld32 $m0, $m6, $m15, 0
 setzi $m5, 2
 and $m6, $m3, $m5
 brz $m6, .Lcopy_u16_source_low
 shr $m0, $m0, 16
.Lcopy_u16_source_low:
 setzi $m5, 65535
 and $m0, $m0, $m5
 mov $m6, $m2
 shr $m6, $m6, 2
 shl $m6, $m6, 2
 ld32 $m1, $m6, $m15, 0
 setzi $m5, 2
 and $m7, $m2, $m5
 brz $m7, .Lcopy_u16_destination_low
 shl $m0, $m0, 16
 setzi $m5, 65535
 and $m1, $m1, $m5
 bri .Lcopy_u16_store
.Lcopy_u16_destination_low:
 setzi $m5, 65535
 shl $m5, $m5, 16
 and $m1, $m1, $m5
.Lcopy_u16_store:
 or $m0, $m0, $m1
 st32 $m0, $m6, $m15, 0
 sub $m4, $m4, 1
 brnz $m4, .Lcopy_u16
.Lcopy_u16_done:
 br $m10
 .size static_copy_u16, .-static_copy_u16




 .section .text.static_patch_repeat_tables,"ax",@progbits
 .globl static_patch_repeat_tables
 .p2align 2
 .type static_patch_repeat_tables,@function
static_patch_repeat_tables:
 .supervisor
 sub $m8, $m5, $m4
 shl $m8, $m8, 2
.Lrepeat_tables:
 ld32 $m0, $m2, $m15, 0
 ld32 $m1, $m2, $m15, 1
 add $m1, $m1, $m8
 ld32 $m6, $m1, $m15, 0
 st32 $m6, $m0, $m15, 0
 add $m2, $m2, 8
 add $m3, $m3, -1
 brnz $m3, .Lrepeat_tables
 br $m9
 .size static_patch_repeat_tables, .-static_patch_repeat_tables

 .section .text.static_patch_repeat_arithmetic,"ax",@progbits
 .globl static_patch_repeat_arithmetic
 .p2align 2
 .type static_patch_repeat_arithmetic,@function
static_patch_repeat_arithmetic:
 .supervisor
 sub $m8, $m5, $m4
.Lrepeat_arithmetic:
 ld32 $m0, $m2, $m15, 0
 ld32 $m1, $m2, $m15, 1
 ld32 $m6, $m2, $m15, 2

 mul $m6, $m6, $m8
 add $m1, $m1, $m6
 st32 $m1, $m0, $m15, 0
 add $m2, $m2, 12
 add $m3, $m3, -1
 brnz $m3, .Lrepeat_arithmetic
 br $m9
 .size static_patch_repeat_arithmetic, .-static_patch_repeat_arithmetic

 .section .text.ipu_stack_static_patch_row,"ax",@progbits


 .globl ipu_stack_static_patch_row
 .p2align 2
 .type ipu_stack_static_patch_row,@function
ipu_stack_static_patch_row:
 .supervisor


 setzi $m0, 24
 cmpult $m0, $m5, $m0
 brz $m0, .Lpatch_row_bulk
 brz $m5, .Lpatch_row_done
.Lpatch_row_next:
 ld32 $m6, $m3, $m15, 0
 ld32 $m0, $m4, $m15, 0
 add $m6, $m6, $m2
 st32 $m0, $m6, $m15, 0
 add $m3, $m3, 4
 add $m4, $m4, 4
 sub $m5, $m5, 1
 brnz $m5, .Lpatch_row_next
.Lpatch_row_done:
 br $m9
.Lpatch_row_bulk:
 add $m11, $m11, -16
 st32 $m2, $m11, $m15, 0
 st32 $m3, $m11, $m15, 1
 st32 $m4, $m11, $m15, 2
 st32 $m5, $m11, $m15, 3
 setzi $m0, .Lpatch_row_worker
 runall $m0, $m11, 0
 sync SYNC_COMPUTE_SET
 add $m11, $m11, 16
 br $m9
 .size ipu_stack_static_patch_row, .-ipu_stack_static_patch_row
 .worker
 .p2align 2
.Lpatch_row_worker:
 ld32 $m2, $mvertex_base, $m15, 0
 ld32 $m3, $mvertex_base, $m15, 1
 ld32 $m4, $mvertex_base, $m15, 2
 ld32 $m5, $mvertex_base, $m15, 3
 get $m7, $WSR
 and $m7, $m7, (0x00000007U)
 shl $m6, $m7, 2
 add $m3, $m3, $m6
 add $m4, $m4, $m6
.Lpatch_row_worker_next:
 ld32 $m6, $m3, $m15, 0
 ld32 $m0, $m4, $m15, 0
 add $m6, $m6, $m2
 st32 $m0, $m6, $m15, 0
 add $m3, $m3, 24
 add $m4, $m4, 24
 add $m7, $m7, 6
 cmpult $m0, $m7, $m5
 brnz $m0, .Lpatch_row_worker_next
 exitz $m15


 .section .text.copy_u64,"ax",@progbits


 .globl copy_u64
 .p2align 2
 .type copy_u64,@function
copy_u64:
 .supervisor
 add $m11, $m11, -16
 st32 $m2, $m11, $m15, 0
 st32 $m3, $m11, $m15, 1
 st32 $m4, $m11, $m15, 2
 st32 $m5, $m11, $m15, 3
 setzi $m0, .Lcopy_u64_worker
 runall $m0, $m11, 0
 sync SYNC_COMPUTE_SET
 add $m11, $m11, 16
 br $m10
 .size copy_u64, .-copy_u64

 .worker
 .p2align 2
.Lcopy_u64_worker:
 ld32 $m2, $mvertex_base, $m15, 0
 ld32 $m3, $mvertex_base, $m15, 1
 ld32 $m5, $mvertex_base, $m15, 2
 ld32 $m6, $mvertex_base, $m15, 3
 get $m4, $WSR
 and $m4, $m4, (0x00000007U)
 cmpult $m7, $m4, $m6
 mul $m8, $m4, $m5
 min $m9, $m4, $m6
 add $m8, $m8, $m9
 shl $m8, $m8, 3
 add $m2, $m2, $m8
 add $m3, $m3, $m8
 add $m5, $m5, $m7
 brz $m5, .Lcopy_u64_worker_done
 {
  rpt $m5, (2f-1f)/8 - 1
  fnop
 }
1:
 {
  ld64step $a0:1, $mzero, $m3+=, 1
  fnop
 }
 {
  st64step $a0:1, $mzero, $m2+=, 1
  fnop
 }
2:
.Lcopy_u64_worker_done:
 exitz $m15

 .section .text.fill_zero_u64,"ax",@progbits


 .globl fill_zero_u64
 .p2align 2
 .type fill_zero_u64,@function
fill_zero_u64:
 .supervisor
 add $m11, $m11, -12
 st32 $m2, $m11, $m15, 0
 st32 $m3, $m11, $m15, 1
 st32 $m4, $m11, $m15, 2
 setzi $m0, .Lfill_zero_u64_worker
 runall $m0, $m11, 0
 sync SYNC_COMPUTE_SET
 add $m11, $m11, 12
 br $m10
 .size fill_zero_u64, .-fill_zero_u64

 .worker
 .p2align 2
.Lfill_zero_u64_worker:
 ld32 $m2, $mvertex_base, $m15, 0
 ld32 $m5, $mvertex_base, $m15, 1
 ld32 $m6, $mvertex_base, $m15, 2
 get $m4, $WSR
 and $m4, $m4, (0x00000007U)
 cmpult $m7, $m4, $m6
 mul $m8, $m4, $m5
 min $m9, $m4, $m6
 add $m8, $m8, $m9
 shl $m8, $m8, 3
 add $m2, $m2, $m8
 add $m5, $m5, $m7
 brz $m5, .Lfill_zero_u64_worker_done
 {
  rpt $m5, (2f-1f)/8 - 1
  fnop
 }
1:
 {
  st64step $azeros, $mzero, $m2+=, 1
  fnop
 }
2:
.Lfill_zero_u64_worker_done:
 exitz $m15

 .macro strided_copy bits, shift
 .section .text.copy_strided_u\bits,"ax",@progbits



 .globl copy_strided_u\bits
 .p2align 2
 .type copy_strided_u\bits,@function
copy_strided_u\bits:
 .supervisor
 add $m11, $m11, -24
 st32 $m2, $m11, $m15, 0
 st32 $m3, $m11, $m15, 1
 st32 $m4, $m11, $m15, 2
 st32 $m5, $m11, $m15, 3
 st32 $m6, $m11, $m15, 4
 st32 $m7, $m11, $m15, 5
 setzi $m0, .Lcopy_strided_u\bits\()_worker
 runall $m0, $m11, 0
 sync SYNC_COMPUTE_SET
 add $m11, $m11, 24
 br $m10
 .size copy_strided_u\bits, .-copy_strided_u\bits

 .worker
 .p2align 2
.Lcopy_strided_u\bits\()_worker:
 ld32 $m2, $mvertex_base, $m15, 0
 ld32 $m3, $mvertex_base, $m15, 1
 ld32 $m5, $mvertex_base, $m15, 2
 ld32 $m6, $mvertex_base, $m15, 3
 ld32 $m7, $mvertex_base, $m15, 4
 ld32 $m8, $mvertex_base, $m15, 5
 get $m4, $WSR
 and $m4, $m4, (0x00000007U)
 cmpult $m9, $m4, $m6
 brz $m9, .Lcopy_strided_u\bits\()_done
 mul $m9, $m4, $m7
 add $m3, $m3, $m9
 mul $m9, $m4, $m8
 add $m2, $m2, $m9
 shl $m1, $m5, \shift


 shl $m0, $m7, 1
 add $m0, $m0, $m7
 shl $m0, $m0, 1
 sub $m0, $m0, $m1
 shl $m9, $m8, 1
 add $m9, $m9, $m8
 shl $m9, $m9, 1
 sub $m1, $m9, $m1
.Lcopy_strided_u\bits\()_row:


 { rpt $m5, 1
   fnop }
 .if \bits == 64
 { ld64step $a0:1, $mzero, $m3+=, 1
   fnop }
 { st64step $a0:1, $mzero, $m2+=, 1
   fnop }
 .else
 { ld32step $a0, $mzero, $m3+=, 1
   fnop }
 { st32step $a0, $mzero, $m2+=, 1
   fnop }
 .endif
 add $m3, $m3, $m0
 add $m2, $m2, $m1
 add $m4, $m4, 6
 cmpult $m9, $m4, $m6
 brnz $m9, .Lcopy_strided_u\bits\()_row
.Lcopy_strided_u\bits\()_done:
 exitz $m15
 .endm

 strided_copy 64, 3
 strided_copy 32, 2

 .section .text.ipu_stack_static_repeat_call,"ax",@progbits




 .globl ipu_stack_static_repeat_call
 .p2align 2
 .type ipu_stack_static_repeat_call,@function
ipu_stack_static_repeat_call:
 .supervisor
.Lrepeat_call:
 setzi $m10, .Lrepeat_return
 br $m3
.Lrepeat_return:
 sub $m2, $m2, 1
 brnz $m2, .Lrepeat_call
 br $m9
 .size ipu_stack_static_repeat_call, .-ipu_stack_static_repeat_call

 .section .text.ipu_stack_static_host_run,"ax",@progbits
 .globl ipu_stack_static_host_run
 .p2align 2
 .type ipu_stack_static_host_run,@function
ipu_stack_static_host_run:
 .supervisor
 add $m11, $m11, -16
 st32 $m4, $m11, $m15, 2
.Lhost_run_next:
 ld32 $m0, $m3, $m15, 1
 shr $m5, $m0, 24
 brz $m5, .Lhost_run_call
 shr $m6, $m0, 20
 and $m6, $m6, 8
 setzi $m1, HOST_PACKET_ADDRESS
 add $m6, $m6, $m1
 ld32 $m7, $m3, $m15, 2
.Lhost_run_packet_copy:
 ld32 $m0, $m7, $m15, 0
 st32 $m0, $m6, $m15, 0
 add $m7, $m7, 4
 add $m6, $m6, 4
 sub $m5, $m5, 1
 brnz $m5, .Lhost_run_packet_copy
.Lhost_run_call:
 st32 $m2, $m11, $m15, 0
 st32 $m3, $m11, $m15, 1
 ld32 $m0, $m11, $m15, 2
 setzi $m10, .Lhost_run_return
 br $m0
.Lhost_run_return:
 ld32 $m2, $m11, $m15, 0
 ld32 $m3, $m11, $m15, 1
 ld32 $m5, $m3, $m15, 1
 shl $m5, $m5, 9
 shr $m5, $m5, 9
 brz $m5, .Lhost_run_advance
 ld32 $m6, $m3, $m15, 0
 setzi $m7, ipu_stack_static_host_staging
.Lhost_run_copy:
 ld32 $m0, $m7, $m15, 0
 st32 $m0, $m6, $m15, 0
 add $m7, $m7, 4
 add $m6, $m6, 4
 sub $m5, $m5, 1
 brnz $m5, .Lhost_run_copy
.Lhost_run_advance:
 add $m3, $m3, HOST_RUN_DESCRIPTOR_BYTES
 sub $m2, $m2, 1
 brnz $m2, .Lhost_run_next
 add $m11, $m11, 16
 br $m9
 .size ipu_stack_static_host_run, .-ipu_stack_static_host_run

 .section .text.ipu_stack_static_sample_cycle,"ax",@progbits
 .globl ipu_stack_static_sample_cycle
 .p2align 2
 .type ipu_stack_static_sample_cycle,@function
ipu_stack_static_sample_cycle:
 .supervisor
 setzi $m5, ipu_stack_static_worker_stack_base
 st32 $m2, $m5, $m15, 0
 setzi $m0, ipu_stack_static_sample_cycle_worker
 runall $m0, $m5, 0
 .long OPCODE_SYNC | SYNC_COMPUTE_SET
 br $m10
 .size ipu_stack_static_sample_cycle, .-ipu_stack_static_sample_cycle

 .section .text.ipu_stack_static_sample_cycle_worker,"ax",@progbits
 .p2align 2
 .type ipu_stack_static_sample_cycle_worker,@function
ipu_stack_static_sample_cycle_worker:
 .worker
 get $m1, $WSR
 and $m1, $m1, 7
 brnz $m1, .Lsample_cycle_exit
 get $m0, $COUNT_L
 ld32 $m2, $mvertex_base, $m15, 0
 st32 $m0, $m2, $m15, 0
.Lsample_cycle_exit:
 exitz $m15
 .size ipu_stack_static_sample_cycle_worker, .-ipu_stack_static_sample_cycle_worker

 .section .text.static_assert_equal_u32,"ax",@progbits


 .globl static_assert_equal_u32
 .p2align 2
 .type static_assert_equal_u32,@function
static_assert_equal_u32:
 .supervisor
.Lassert_equal_u32_next:
 ld32 $m0, $m3, $m15, 0
 ld32 $m1, $m4, $m15, 0
 xor $m0, $m0, $m1
 brnz $m0, .Lassert_equal_u32_failed
 add $m3, $m3, 4
 add $m4, $m4, 4
 sub $m5, $m5, 1
 brnz $m5, .Lassert_equal_u32_next
 br $m10
.Lassert_equal_u32_failed:
 bri .Lassert_equal_u32_failed
 .size static_assert_equal_u32, .-static_assert_equal_u32

 .section .text.static_worker_delay,"ax",@progbits


 .globl static_worker_delay
 .p2align 2
 .type static_worker_delay,@function
static_worker_delay:
 .supervisor
 add $m11, $m11, -8
 st32 $m4, $m11, $m15, 0
 setzi $m0, .Lworker_delay
 runall $m0, $m11, 0
 .long OPCODE_SYNC | SYNC_COMPUTE_SET
 add $m11, $m11, 8
 br $m10
 .size static_worker_delay, .-static_worker_delay

 .worker
 .p2align 2
.Lworker_delay:
 ld32 $m0, $mvertex_base, $m15, 0
.Lworker_delay_next:
 sub $m0, $m0, 1
 brnz $m0, .Lworker_delay_next
 exitz $m15

 .section .text.ipu_stack_static_complete,"ax",@progbits
 .globl ipu_stack_static_complete
 .p2align 2
 .type ipu_stack_static_complete,@function
ipu_stack_static_complete:
 .supervisor
 setzi $m0, 1
 setzi $m1, ipu_stack_static_completion
 st32 $m0, $m1, $m15, 0
 zero $m0


 .globl ipu_stack_static_completed
ipu_stack_static_completed:
 br $m0
 .size ipu_stack_static_complete, .-ipu_stack_static_complete
# 2 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S" 2
# 1 "/srv/home/gc-sdk/ipu-stack/device/worker_support.S" 1
 .text





 .globl __worker_stack_max_growth_plus_one
 .set __worker_stack_max_growth_plus_one, 0x100 + 1

 .section .text._stackoverflow,"ax",@progbits
 .globl _stackoverflow
 .p2align 2
 .type _stackoverflow,@function
_stackoverflow:
 .worker
 trap 0
 .size _stackoverflow, .-_stackoverflow
# 3 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S" 2
 .text
 .allow_optimizations
 .file "3"
 .section .text.__runCodelet_AddF16,"ax",@progbits
 .globl __runCodelet_AddF16 # -- Begin function __runCodelet_AddF16
 .p2align 2
 .type __runCodelet_AddF16,@function
__runCodelet_AddF16: # @__runCodelet_AddF16
 .worker
.Lcode0_func_begin0:
 # %bb.0: # %entry
 setzi $m6, 32
 cmpult $m6, $m6, __worker_stack_max_growth_plus_one
 brz $m6, _stackoverflow
 add $m11, $m12, -32
 get $m0, 1
 ld32 $m10, $m13, $m15, 3
 and $m6, $m0, 7
 ld32 $m1, $m13, $m15, 4
 ld32 $m3, $m13, $m15, 5
 st32 $m10, $m11, $m15, 7 # 4-byte Folded Spill
 brz $m10, .Lcode0_BB0_18
 # %bb.1: # %entry
 and $m0, $m10, 3
 brnz $m0, .Lcode0_BB0_18
 # %bb.2: # %entry
 and $m0, $m1, 3
 brnz $m0, .Lcode0_BB0_18
 # %bb.3: # %entry
 and $m0, $m3, 3
 brnz $m0, .Lcode0_BB0_18
 # %bb.4: # %land.lhs.true12.i
 ld32 $m0, $m13, $m15, 0
 ld32 $m2, $m13, $m15, 1
 or $m5, $m2, $m0
 ld32 $m4, $m13, $m15, 2
 or $m5, $m5, $m4
 and $m5, $m5, 6
 brz $m5, .Lcode0_BB0_5
.Lcode0_BB0_18: # %if.end62.i
 shr $m4, $m10, 1
 brz $m6, .Lcode0_BB0_20
 # %bb.19: # %if.end62.i
 cmpult $m0, $m6, $m4
 brnz $m0, .Lcode0_BB0_20
.Lcode0_BB0_72: # %_ZN6AddF167computeEj.exit
 exitz $m15
.Lcode0_BB0_20: # %if.end68.i
 st32 $m6, $m11, $m15, 2 # 4-byte Folded Spill
 and $m2, $m10, 1
 brnz $m2, .Lcode0_BB0_50
 # %bb.21: # %if.end68.i
 and $m0, $m1, 1
 brnz $m0, .Lcode0_BB0_50
 # %bb.22: # %if.end68.i
 and $m0, $m3, 1
 brnz $m0, .Lcode0_BB0_50
 # %bb.23: # %if.then77.i
 cmpne $m2, $m1, $m10
 ld32 $m0, $m13, $m15, 0
 st32 $m0, $m11, $m15, 6 # 4-byte Folded Spill
 ld32 $m7, $m13, $m15, 1
 ld32 $m0, $m13, $m15, 2
 st32 $m0, $m11, $m15, 5 # 4-byte Folded Spill
 cmpne $m0, $m3, $m10
 brnz $m2, .Lcode0_BB0_28
 # %bb.24: # %if.then77.i
 brnz $m0, .Lcode0_BB0_28
 # %bb.25: # %for.cond89.preheader.i
 ld32 $m5, $m11, $m15, 2 # 4-byte Folded Reload
 cmpult $m0, $m5, $m4
 brz $m0, .Lcode0_BB0_72
 # %bb.26: # %for.body93.i.preheader
 xnor $m0, $m5, $m15
 add $m0, $m0, $m4
 setzi $m1, 43691
 sort4x16lo $m2, $m0, $m15
 shr $m0, $m0, 16
 mul $m3, $m2, $m1
 mul $m1, $m0, $m1
 shr $m3, $m3, 16
 add $m1, $m1, $m3
 setzi $m3, 43690
 mul $m2, $m2, $m3
 mul $m0, $m0, $m3
 sort4x16lo $m3, $m1, $m15
 shr $m1, $m1, 16
 add $m2, $m2, $m3
 add $m0, $m0, $m1
 shr $m1, $m2, 16
 add $m0, $m0, $m1
 shr $m0, $m0, 2
 shl $m3, $m5, 2
 ld32 $m1, $m11, $m15, 5 # 4-byte Folded Reload
 add $m1, $m1, $m3
 add $m2, $m7, $m3
 ld32 $m4, $m11, $m15, 6 # 4-byte Folded Reload
 add $m3, $m4, $m3
.Lcode0_BB0_27: # %for.body93.i
                                        # =>This Inner Loop Header: Depth=1
 ld32step $a0, $m15, $m3+=, 6
 ld32step $a1, $m15, $m2+=, 6
 f16v2add $a0, $a0, $a1
 st32step $a0, $m15, $m1+=, 6
 brnzdec $m0, .Lcode0_BB0_27
 bri .Lcode0_BB0_72
.Lcode0_BB0_50: # %if.end180.i
 st32 $m2, $m11, $m15, 1 # 4-byte Folded Spill
 ld32 $m0, $m11, $m15, 2 # 4-byte Folded Reload
 shl $m4, $m0, 1
 add $m6, $m1, $m4
 mov $m0, $m4
.Lcode0_BB0_51: # %while.cond.i433.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m2, $m0, $m1
 sub $m0, $m0, $m1
 sub $m6, $m6, $m1
 brz $m2, .Lcode0_BB0_51
 # %bb.52: # %while.cond.i438.i.preheader
 add $m7, $m3, $m4
 mov $m0, $m4
.Lcode0_BB0_53: # %while.cond.i438.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m2, $m0, $m3
 sub $m0, $m0, $m3
 sub $m7, $m7, $m3
 brz $m2, .Lcode0_BB0_53
 # %bb.54: # %for.cond188.preheader.i
 or $m0, $m4, 1
 cmpult $m0, $m0, $m10
 brz $m0, .Lcode0_BB0_65
 # %bb.55: # %for.body192.lr.ph.i
 shl $m8, $m1, 1
 shl $m9, $m3, 1
 add $m0, $m8, 2
 st32 $m0, $m11, $m15, 6 # 4-byte Folded Spill
 add $m0, $m9, 2
 st32 $m0, $m11, $m15, 5 # 4-byte Folded Spill
 add $m0, $m1, 12
 st32 $m0, $m11, $m15, 4 # 4-byte Folded Spill
 add $m0, $m3, 12
 st32 $m0, $m11, $m15, 3 # 4-byte Folded Spill
.Lcode0_BB0_56: # %for.body192.i
                                        # =>This Loop Header: Depth=1
                                        # Child Loop BB0_57 Depth 2
                                        # Child Loop BB0_59 Depth 2
                                        # Child Loop BB0_61 Depth 2
                                        # Child Loop BB0_63 Depth 2
 ld32 $m5, $m13, $m15, 0
 shl $m0, $m6, 1
 ldb16 $a0, $m5, $m15, $m6
 add $m10, $m6, 1
 ld32 $m2, $m11, $m15, 6 # 4-byte Folded Reload
 add $m0, $m2, $m0
.Lcode0_BB0_57: # %while.cond.i443.i
                                        # Parent Loop BB0_56 Depth=1
                                        # => This Inner Loop Header: Depth=2
 cmpult $m2, $m10, $m1
 sub $m10, $m10, $m1
 sub $m0, $m0, $m8
 brz $m2, .Lcode0_BB0_57
 # %bb.58: # %_ZN6AddF164wrapEjj.exit444.i
                                        # in Loop: Header=BB0_56 Depth=1
 ld32 $m10, $m13, $m15, 1
 ldb16 $a1, $m5, $m0, 0
 shl $m2, $m7, 1
 ldb16 $a2, $m10, $m15, $m7
 add $m0, $m7, 1
 ld32 $m5, $m11, $m15, 5 # 4-byte Folded Reload
 add $m5, $m5, $m2
.Lcode0_BB0_59: # %while.cond.i448.i
                                        # Parent Loop BB0_56 Depth=1
                                        # => This Inner Loop Header: Depth=2
 cmpult $m2, $m0, $m3
 sub $m0, $m0, $m3
 sub $m5, $m5, $m9
 brz $m2, .Lcode0_BB0_59
 # %bb.60: # %_ZN6AddF164wrapEjj.exit449.i
                                        # in Loop: Header=BB0_56 Depth=1
 {
  ldb16 $a1, $m10, $m5, 0
  sort4x16lo $a0, $a0, $a1
 }
 {
  ld32 $m0, $m13, $m15, 2
  sort4x16lo $a1, $a2, $a1
 }
 {
  shl $m2, $m4, 1
  f16v2add $a0, $a0, $a1
 }
 st32 $a0, $m0, $m2, 0
 add $m0, $m6, 12
 ld32 $m2, $m11, $m15, 4 # 4-byte Folded Reload
 add $m6, $m2, $m6
.Lcode0_BB0_61: # %while.cond.i453.i
                                        # Parent Loop BB0_56 Depth=1
                                        # => This Inner Loop Header: Depth=2
 cmpult $m2, $m0, $m1
 sub $m0, $m0, $m1
 sub $m6, $m6, $m1
 brz $m2, .Lcode0_BB0_61
 # %bb.62: # %_ZN6AddF164wrapEjj.exit454.i
                                        # in Loop: Header=BB0_56 Depth=1
 add $m0, $m7, 12
 ld32 $m2, $m11, $m15, 3 # 4-byte Folded Reload
 add $m7, $m2, $m7
 ld32 $m10, $m11, $m15, 7 # 4-byte Folded Reload
.Lcode0_BB0_63: # %while.cond.i458.i
                                        # Parent Loop BB0_56 Depth=1
                                        # => This Inner Loop Header: Depth=2
 cmpult $m2, $m0, $m3
 sub $m0, $m0, $m3
 sub $m7, $m7, $m3
 brz $m2, .Lcode0_BB0_63
 # %bb.64: # %_ZN6AddF164wrapEjj.exit459.i
                                        # in Loop: Header=BB0_56 Depth=1
 add $m4, $m4, 12
 or $m0, $m4, 1
 cmpult $m0, $m0, $m10
 brnz $m0, .Lcode0_BB0_56
.Lcode0_BB0_65: # %for.cond.cleanup191.i
 ld32 $m0, $m11, $m15, 2 # 4-byte Folded Reload
 brnz $m0, .Lcode0_BB0_72
 # %bb.66: # %for.cond.cleanup191.i
 ld32 $m0, $m11, $m15, 1 # 4-byte Folded Reload
 brz $m0, .Lcode0_BB0_72
 # %bb.67: # %if.then224.i
 shl $m2, $m10, 1
 shl $m4, $m1, 1
 add $m0, $m10, -1
 add $m5, $m2, $m4
 add $m5, $m5, -2
 mov $m6, $m0
.Lcode0_BB0_68: # %while.cond.i463.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m7, $m6, $m1
 sub $m6, $m6, $m1
 sub $m5, $m5, $m4
 brz $m7, .Lcode0_BB0_68
 # %bb.69: # %_ZN6AddF164wrapEjj.exit464.i
 shl $m4, $m3, 1
 add $m1, $m2, $m4
 add $m1, $m1, -2
 ld32 $m2, $m13, $m15, 0
 ldb16 $a0, $m2, $m5, 0
 mov $m2, $m0
.Lcode0_BB0_70: # %while.cond.i468.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m5, $m2, $m3
 sub $m2, $m2, $m3
 sub $m1, $m1, $m4
 brz $m5, .Lcode0_BB0_70
 # %bb.71: # %_ZN6AddF164wrapEjj.exit469.i
 ld32 $m2, $m13, $m15, 1
 shl $m0, $m0, 1
 ldb16 $a1, $m2, $m1, 0
 {
  ld32 $m1, $m13, $m15, 2
  f16v2add $a0, $a0, $a1
 }
 {
  andc $m0, $m0, 3
  sort4x16lo $a0, $a0, $azero
 }
 ld32 $m2, $m1, $m0, 0
 setzi $m3, 65535
 andc $m2, $m2, $m3
 mov $m3, $a0
 or $m2, $m2, $m3
 st32 $m2, $m1, $m0, 0
 exitz $m15
.Lcode0_BB0_5: # %if.then.i
 cmpne $m5, $m1, $m10
 brnz $m5, .Lcode0_BB0_9
 # %bb.6: # %if.then.i
 cmpne $m5, $m3, $m10
 brnz $m5, .Lcode0_BB0_9
 # %bb.7: # %if.then19.i
 shr $m1, $m10, 2
 cmpult $m3, $m6, $m1
 mov $m7, $m6
 brz $m3, .Lcode0_BB0_72
 # %bb.8: # %if.end.i.i
 sub $m1, $m1, $m7
 add $m1, $m1, 5
 setzi $m3, 43691
 sort4x16lo $m5, $m1, $m15
 shr $m1, $m1, 16
 mul $m6, $m5, $m3
 mul $m3, $m1, $m3
 shr $m6, $m6, 16
 add $m3, $m3, $m6
 setzi $m6, 43690
 mul $m5, $m5, $m6
 mul $m1, $m1, $m6
 sort4x16lo $m6, $m3, $m15
 shr $m3, $m3, 16
 add $m5, $m5, $m6
 add $m1, $m1, $m3
 shr $m3, $m5, 16
 shl $m5, $m7, 3
 add $m1, $m1, $m3
 add $m0, $m0, $m5
 add $m2, $m2, $m5
 add $m3, $m4, $m5
 shr $m1, $m1, 2
 #APP
 {
  rpt $m1, 3
  fnop
 }

 {
  ld64step $ap0, $m15, $m0+=, 6
  fnop
 }

 {
  ld64step $ap1, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v4add $ap0, $ap0, $ap1
 }

 {
  st64step $ap0, $m15, $m3+=, 6
  fnop
 }


 #NO_APP
 exitz $m15
.Lcode0_BB0_28: # %if.else.i
 cmpeq $m2, $m1, $m10
 ld32 $m6, $m11, $m15, 2 # 4-byte Folded Reload
 brnz $m2, .Lcode0_BB0_30
 # %bb.29: # %if.else.i
 brnz $m0, .Lcode0_BB0_39
.Lcode0_BB0_30: # %land.lhs.true103.i
 cmpult $m8, $m1, $m3
 mov $m0, $m3
 movnz $m0, $m8, $m1
 sub $m8, 0, $m0
 mov $m9, $m10
.Lcode0_BB0_31: # %while.cond.i408.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m10, $m9, $m0
 sub $m9, $m9, $m0
 add $m8, $m8, $m0
 brz $m10, .Lcode0_BB0_31
 # %bb.32: # %_ZN6AddF164wrapEjj.exit409.i
 ld32 $m5, $m11, $m15, 7 # 4-byte Folded Reload
 cmpne $m0, $m5, $m8
 brnz $m0, .Lcode0_BB0_39
 # %bb.33: # %if.then111.i
 cmpult $m0, $m5, 2
 mov $m8, $m6
 brnz $m0, .Lcode0_BB0_72
 # %bb.34: # %for.cond138.preheader.lr.ph.i
 mov $m0, $m15
 movnz $m1, $m2, $m3
 shr $m1, $m1, 1
 xnor $m3, $m8, $m15
 add $m3, $m3, $m1
 setzi $m5, 43691
 sort4x16lo $m9, $m3, $m15
 shr $m3, $m3, 16
 mul $m10, $m9, $m5
 mul $m5, $m3, $m5
 shr $m10, $m10, 16
 add $m5, $m5, $m10
 setzi $m10, 43690
 mul $m9, $m9, $m10
 mul $m3, $m3, $m10
 sort4x16lo $m10, $m5, $m15
 shr $m5, $m5, 16
 add $m9, $m9, $m10
 add $m3, $m3, $m5
 shr $m5, $m9, 16
 mov $m9, $m7
 add $m3, $m3, $m5
 ld32 $m5, $m11, $m15, 6 # 4-byte Folded Reload
 movnz $m9, $m2, $m5
 movnz $m5, $m2, $m7
 shl $m2, $m8, 2
 shr $m7, $m3, 2
 add $m3, $m5, $m2
 st32 $m3, $m11, $m15, 7 # 4-byte Folded Spill
 ld32 $m3, $m11, $m15, 5 # 4-byte Folded Reload
 add $m3, $m3, $m2
 shl $m5, $m1, 2
 add $m6, $m9, $m2
 add $m7, $m7, 1
 bri .Lcode0_BB0_35
.Lcode0_BB0_38: # %for.cond.cleanup140.i
                                        # in Loop: Header=BB0_35 Depth=1
 add $m0, $m0, $m1
 cmpult $m2, $m0, $m4
 add $m3, $m3, $m5
 add $m6, $m6, $m5
 ld32 $m8, $m11, $m15, 2 # 4-byte Folded Reload
 brz $m2, .Lcode0_BB0_72
.Lcode0_BB0_35: # %for.cond138.preheader.i
                                        # =>This Loop Header: Depth=1
                                        # Child Loop BB0_37 Depth 2
 cmpult $m2, $m8, $m1
 brz $m2, .Lcode0_BB0_38
 # %bb.36: # %for.body141.i.preheader
                                        # in Loop: Header=BB0_35 Depth=1
 mov $m8, $m7
 mov $m9, $m6
 mov $m10, $m3
 ld32 $m2, $m11, $m15, 7 # 4-byte Folded Reload
 add $m8, $m8, -1
.Lcode0_BB0_37: # %for.body141.i
                                        # Parent Loop BB0_35 Depth=1
                                        # => This Inner Loop Header: Depth=2
 ld32step $a0, $m15, $m9+=, 6
 ld32step $a1, $m15, $m2+=, 6
 f16v2add $a0, $a0, $a1
 st32step $a0, $m15, $m10+=, 6
 brnzdec $m8, .Lcode0_BB0_37
 bri .Lcode0_BB0_38
.Lcode0_BB0_9: # %if.end.i
 cmpeq $m7, $m1, $m10
 brnz $m7, .Lcode0_BB0_11
 # %bb.10: # %if.end.i
 cmpne $m5, $m3, $m10
 brnz $m5, .Lcode0_BB0_18
.Lcode0_BB0_11: # %land.lhs.true28.i
 st32 $m6, $m11, $m15, 2 # 4-byte Folded Spill
 cmpult $m6, $m1, $m3
 mov $m5, $m3
 movnz $m5, $m6, $m1
 sub $m6, 0, $m5
 mov $m8, $m10
.Lcode0_BB0_12: # %while.cond.i.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m9, $m8, $m5
 sub $m8, $m8, $m5
 add $m6, $m6, $m5
 brz $m9, .Lcode0_BB0_12
 # %bb.13: # %_ZN6AddF164wrapEjj.exit.i
 cmpne $m5, $m10, $m6
 ld32 $m6, $m11, $m15, 2 # 4-byte Folded Reload
 brnz $m5, .Lcode0_BB0_18
 # %bb.14: # %if.then32.i
 mov $m5, $m15
 movnz $m1, $m7, $m3
 shr $m3, $m1, 2
 st32 $m7, $m11, $m15, 5 # 4-byte Folded Spill
 mov $m7, $m6
 sub $m6, $m3, $m7
 add $m6, $m6, 5
 setzi $m8, 43691
 sort4x16lo $m9, $m6, $m15
 shr $m6, $m6, 16
 mul $m10, $m9, $m8
 mul $m8, $m6, $m8
 shr $m10, $m10, 16
 add $m8, $m8, $m10
 setzi $m10, 43690
 mul $m9, $m9, $m10
 mul $m10, $m6, $m10
 sort4x16lo $m6, $m8, $m15
 shr $m8, $m8, 16
 add $m9, $m9, $m6
 mov $m6, $m2
 add $m8, $m10, $m8
 st32 $m8, $m11, $m15, 4 # 4-byte Folded Spill
 ld32 $m10, $m11, $m15, 7 # 4-byte Folded Reload
 shr $m9, $m9, 16
 ld32 $m8, $m11, $m15, 5 # 4-byte Folded Reload
 movnz $m6, $m8, $m0
 st32 $m6, $m11, $m15, 6 # 4-byte Folded Spill
 movnz $m0, $m8, $m2
 shl $m2, $m7, 3
 ld32 $m6, $m11, $m15, 4 # 4-byte Folded Reload
 add $m6, $m6, $m9
 add $m0, $m0, $m2
 st32 $m0, $m11, $m15, 5 # 4-byte Folded Spill
 shr $m6, $m6, 2
 shl $m8, $m1, 1
 bri .Lcode0_BB0_15
.Lcode0_BB0_17: # %_ZL8addQuadsPKDhS0_PDhjj.exit404.i
                                        # in Loop: Header=BB0_15 Depth=1
 add $m5, $m5, $m1
 cmpult $m0, $m5, $m10
 add $m2, $m2, $m8
 ld32 $m7, $m11, $m15, 2 # 4-byte Folded Reload
 brz $m0, .Lcode0_BB0_72
.Lcode0_BB0_15: # %for.body.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m9, $m7, $m3
 brz $m9, .Lcode0_BB0_17
 # %bb.16: # %if.end.i403.i
                                        # in Loop: Header=BB0_15 Depth=1
 ld32 $m0, $m11, $m15, 6 # 4-byte Folded Reload
 add $m9, $m0, $m2
 add $m10, $m4, $m2
 ld32 $m0, $m11, $m15, 5 # 4-byte Folded Reload
 #APP
 {
  rpt $m6, 3
  fnop
 }

 {
  ld64step $ap0, $m15, $m9+=, 6
  fnop
 }

 {
  ld64step $ap1, $m15, $m0+=, 6
  fnop
 }

 {
  nop
  f16v4add $ap0, $ap0, $ap1
 }

 {
  st64step $ap0, $m15, $m10+=, 6
  fnop
 }


 #NO_APP
 ld32 $m10, $m11, $m15, 7 # 4-byte Folded Reload
 bri .Lcode0_BB0_17
.Lcode0_BB0_39: # %if.else154.i
 shr $m1, $m1, 1
 add $m2, $m1, $m6
 mov $m0, $m6
.Lcode0_BB0_40: # %while.cond.i413.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m8, $m0, $m1
 sub $m0, $m0, $m1
 sub $m2, $m2, $m1
 brz $m8, .Lcode0_BB0_40
 # %bb.41: # %_ZN6AddF164wrapEjj.exit414.i
 shr $m3, $m3, 1
 add $m8, $m3, $m6
 mov $m0, $m6
.Lcode0_BB0_42: # %while.cond.i418.i
                                        # =>This Inner Loop Header: Depth=1
 cmpult $m9, $m0, $m3
 sub $m0, $m0, $m3
 sub $m8, $m8, $m3
 brz $m9, .Lcode0_BB0_42
 # %bb.43: # %for.cond160.preheader.i
 cmpult $m0, $m6, $m4
 brz $m0, .Lcode0_BB0_72
 # %bb.44: # %for.body164.i.preheader
 xnor $m0, $m6, $m15
 add $m0, $m0, $m4
 setzi $m4, 43691
 sort4x16lo $m9, $m0, $m15
 shr $m0, $m0, 16
 mul $m10, $m9, $m4
 mul $m4, $m0, $m4
 shr $m10, $m10, 16
 add $m4, $m4, $m10
 setzi $m10, 43690
 sort4x16lo $m5, $m4, $m15
 mul $m9, $m9, $m10
 shr $m4, $m4, 16
 mul $m0, $m0, $m10
 add $m9, $m9, $m5
 add $m0, $m0, $m4
 shr $m4, $m9, 16
 add $m0, $m0, $m4
 shr $m0, $m0, 2
 add $m4, $m1, 6
 add $m9, $m3, 6
.Lcode0_BB0_45: # %for.body164.i
                                        # =>This Loop Header: Depth=1
                                        # Child Loop BB0_46 Depth 2
                                        # Child Loop BB0_48 Depth 2
 ld32 $m5, $m11, $m15, 6 # 4-byte Folded Reload
 ld32 $a0, $m5, $m15, $m2
 ld32 $a1, $m7, $m15, $m8
 {
  mov $m5, $m6
  f16v2add $a0, $a0, $a1
 }
 ld32 $m10, $m11, $m15, 5 # 4-byte Folded Reload
 st32 $a0, $m10, $m15, $m6
 add $m10, $m2, 6
 add $m2, $m4, $m2
.Lcode0_BB0_46: # %while.cond.i423.i
                                        # Parent Loop BB0_45 Depth=1
                                        # => This Inner Loop Header: Depth=2
 cmpult $m6, $m10, $m1
 sub $m10, $m10, $m1
 sub $m2, $m2, $m1
 brz $m6, .Lcode0_BB0_46
 # %bb.47: # %_ZN6AddF164wrapEjj.exit424.i
                                        # in Loop: Header=BB0_45 Depth=1
 add $m10, $m8, 6
 add $m8, $m9, $m8
.Lcode0_BB0_48: # %while.cond.i428.i
                                        # Parent Loop BB0_45 Depth=1
                                        # => This Inner Loop Header: Depth=2
 cmpult $m6, $m10, $m3
 sub $m10, $m10, $m3
 sub $m8, $m8, $m3
 brz $m6, .Lcode0_BB0_48
 # %bb.49: # %_ZN6AddF164wrapEjj.exit429.i
                                        # in Loop: Header=BB0_45 Depth=1
 mov $m6, $m5
 add $m6, $m6, 6
 brnzdec $m0, .Lcode0_BB0_45
 bri .Lcode0_BB0_72
.Lcode0_func_end0:
 .size __runCodelet_AddF16, .Lcode0_func_end0-__runCodelet_AddF16
 .section .stack_sizes,"o",@progbits,.text.__runCodelet_AddF16
 .long .Lcode0_func_begin0
 .byte 32
 .section .text.__runCodelet_AddF16,"ax",@progbits
                                        # -- End function
 .ident "clang version 16.0.0 (git@github.com:Software-GCAI/llvm-project.git 6343a843cd5af31429c62a83b6ba249a74d36969)"
 .section ".note.GNU-stack","",@progbits
 .addrsig





# 1 "/srv/home/gc-sdk/ipu-stack/device/worker_call.S" 1




 .text
 .allow_optimizations
 .set SYNC_COMPUTE_SET, (2)

 .section .text.add_f16,"ax",@progbits
 .globl add_f16
 .p2align 2
 .type add_f16,@function
add_f16:
 .supervisor
 add $m11, $m11, -48
 .set argument_index, 0
 .irp argument, $m3,$m4,$m2,$m5,$m6,$m7
 st32 \argument, $m11, $m15, argument_index
 .set argument_index, argument_index + 1
 .endr



 setzi $m0, __runCodelet_AddF16

1:
 runall $m0, $m11, 0
 sync SYNC_COMPUTE_SET



 add $m11, $m11, 48
 br $m10
 .size add_f16, .-add_f16
# 638 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S" 2




 .text
 .allow_optimizations
 .file "3"
 .section .text.__runCodelet_LayerNormF16,"ax",@progbits
 .globl __runCodelet_LayerNormF16 # -- Begin function __runCodelet_LayerNormF16
 .p2align 2
 .type __runCodelet_LayerNormF16,@function
__runCodelet_LayerNormF16: # @__runCodelet_LayerNormF16
 .worker
.Lcode1_func_begin0:
 # %bb.0: # %entry
 setzi $m6, 16
 cmpult $m6, $m6, __worker_stack_max_growth_plus_one
 brz $m6, _stackoverflow
 add $m11, $m12, -16
 get $m0, 1
 ld32 $m4, $m13, $m15, 7
 and $m0, $m0, 7
 ld32 $m1, $m13, $m15, 6
 ld32 $m2, $m13, $m15, 0
 ld32 $m3, $m13, $m15, 5
 brz $m4, .Lcode1_BB0_6
 # %bb.1: # %for.body.preheader.i
 ld64 $ap0, $m1, $m15, 0
 {
  ld64 $ap1, $m1, $m15, 1
  f32v2add $ap0, $ap0, $apzero
 }
 {
  ld64 $ap1, $m1, $m15, 2
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 3
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 4
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 5
  f32v2add $ap0, $ap0, $ap1
 }
 {
  cmpeq $m4, $m4, 1
  f32v2add $ap0, $ap0, $ap1
 }
 {
  st32 $m3, $m11, $m15, 1
  f32add $a0, $a0, $a1
 }
 ld32 $a1, $m11, $m15, 1
 f32fromui32 $a1, $a1
 {
  brz $m4, .Lcode1_BB0_2
  f32div $a0, $a0, $a1
 }
 # %bb.12: # %if.then11.i
 cmpult $m4, $m3, 96
 brnz $m4, .Lcode1_BB0_15
 # %bb.13: # %if.then11.i
 or $m4, $m3, $m2
 and $m4, $m4, 7
 brnz $m4, .Lcode1_BB0_15
 # %bb.14: # %if.then.i73.i
 mov $m4, $m15
 {
  shr $m3, $m3, 2
  f32sub $a7, $azero, $a0
 }
 sub $m5, $m3, $m0
 add $m3, $m11, 8
 add $m5, $m5, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 mul $m8, $m7, $m6
 mul $m6, $m5, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m5, $m5, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m5, $m5, $m6
 shr $m6, $m7, 16
 shl $m7, $m0, 3
 add $m5, $m5, $m6
 add $m2, $m2, $m7
 shr $m5, $m5, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 mov $a6, $a7
 {
  rpt $m5, 5
  fnop
 }

 {
  ld64step $ap2, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v4sqacc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m3, $m15, 0

 #NO_APP
 ld64 $ap3, $m11, $m15, 1
 bri .Lcode1_BB0_18
.Lcode1_BB0_6: # %if.then.i
 cmpult $m4, $m3, 96
 brnz $m4, .Lcode1_BB0_9
 # %bb.7: # %if.then.i
 or $m4, $m3, $m2
 and $m4, $m4, 7
 brnz $m4, .Lcode1_BB0_9
 # %bb.8: # %if.then.i.i
 mov $m4, $m15
 shr $m5, $m3, 3
 add $m3, $m11, 8
 sub $m5, $m5, $m0
 add $m5, $m5, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 mul $m8, $m7, $m6
 mul $m6, $m5, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m5, $m5, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m5, $m5, $m6
 shr $m6, $m7, 16
 shl $m7, $m0, 4
 add $m5, $m5, $m6
 add $m2, $m2, $m7
 shr $m5, $m5, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 {
  rpt $m5, 2
  fnop
 }

 {
  ld64step $ap0, $m15, $m2+=, 1
  fnop
 }

 {
  ld64step $ap1, $m15, $m2+=, 11
  fnop
 }

 {
  nop
  f16v8acc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m3, $m15, 0

 #NO_APP
 ld64 $ap2, $m11, $m15, 1
 st64 $ap2, $m1, $m15, $m0
 exitz $m15
.Lcode1_BB0_2: # %for.body20.preheader.i
 {
  ld64 $ap1, $m1, $m15, 6
  setzi $a4, 407485
 }
 {
  and $m6, $m3, 3
  f32v2add $ap1, $ap1, $apzero
 }
 {
  ld32 $m5, $m13, $m15, 1
  or $a4, $a4, 897581056
 }
 ld32 $m4, $m13, $m15, 2
 ld64 $ap3, $m1, $m15, 7
 {
  ld64 $ap3, $m1, $m15, 8
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 9
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 10
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 11
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld32 $m1, $m13, $m15, 3
  f32v2add $ap1, $ap1, $ap3
 }
 f32add $a2, $a2, $a3
 f32div $a1, $a2, $a1
 f32add $a1, $a1, $a4
 #APP
 f32oorx $a1, $a1
 #NO_APP
 brnz $m6, .Lcode1_BB0_19
 # %bb.3: # %land.lhs.true.i.i
 or $m6, $m5, $m2
 or $m6, $m6, $m4
 or $m6, $m6, $m1
 and $m6, $m6, 6
 brz $m6, .Lcode1_BB0_4
.Lcode1_BB0_19: # %if.end18.i.i
 shr $m6, $m3, 1
 cmpult $m3, $m0, $m6
 brz $m3, .Lcode1_BB0_21
 # %bb.20: # %if.end22.i.i
 mov $m3, $m15
 {
  sub $m6, $m6, $m0
  f32sub $a0, $azero, $a0
 }
 add $m7, $m6, 5
 st32 $a0, $m11, $m15, 2
 setzi $m8, 43691
 st32 $a1, $m11, $m15, 3
 sort4x16lo $m9, $m7, $m15
 add $m6, $m11, 8
 shr $m7, $m7, 16
 shl $m10, $m0, 2
 add $m0, $m2, $m10
 add $m2, $m5, $m10
 add $m4, $m4, $m10
 add $m1, $m1, $m10
 mul $m5, $m9, $m8
 mul $m8, $m7, $m8
 shr $m5, $m5, 16
 add $m5, $m8, $m5
 setzi $m8, 43690
 mul $m9, $m9, $m8
 mul $m7, $m7, $m8
 sort4x16lo $m8, $m5, $m15
 shr $m5, $m5, 16
 add $m8, $m9, $m8
 add $m5, $m7, $m5
 shr $m7, $m8, 16
 add $m5, $m5, $m7
 shr $m5, $m5, 2
 #APP
 ld32 $a6, $m6, $m15, 0
 ld32 $a7, $m6, $m15, 1
 {
  rpt $m5, 9
  fnop
 }

 {
  ld32step $a0, $m15, $m0+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  ld32step $a2, $m15, $m2+=, 6
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f16v2tof32 $ap1, $a2
 }

 {
  ld32step $a4, $m15, $m4+=, 6
  f32v2mul $ap0, $ap0, $ap1
 }

 {
  nop
  f16v2tof32 $ap1, $a4
 }

 {
  nop
  f32v2add $ap0, $ap0, $ap1
 }

 {
  nop
  f32v2tof16 $a0, $ap0
 }

 {
  st32step $a0, $m15, $m1+=, 6
  fnop
 }


 #NO_APP
.Lcode1_BB0_21: # %_ZN12LayerNormF167computeEj.exit
 exitz $m15
.Lcode1_BB0_9: # %if.end.i.i
 {
  shr $m4, $m3, 1
  zero $ap2
 }
 cmpult $m3, $m0, $m4
 brz $m3, .Lcode1_BB0_11
 # %bb.10: # %if.end6.i.i
 mov $m3, $m15
 sub $m4, $m4, $m0
 add $m4, $m4, 5
 setzi $m5, 43691
 sort4x16lo $m6, $m4, $m15
 shr $m4, $m4, 16
 mul $m7, $m6, $m5
 mul $m5, $m4, $m5
 shr $m7, $m7, 16
 add $m5, $m5, $m7
 setzi $m7, 43690
 mul $m6, $m6, $m7
 mul $m4, $m4, $m7
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 add $m6, $m6, $m7
 add $m4, $m4, $m5
 shr $m5, $m6, 16
 shl $m6, $m0, 2
 add $m4, $m4, $m5
 add $m2, $m2, $m6
 shr $m4, $m4, 2
 #APP
 {
  rpt $m4, 2
  fnop
 }

 {
  ld32step $a0, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap2, $ap2, $ap0
 }


 #NO_APP
.Lcode1_BB0_11: # %_ZL7normSumPKDhS0_jjfb.exit.i
 st64 $ap2, $m1, $m15, $m0
 exitz $m15
.Lcode1_BB0_15: # %if.end.i76.i
 shr $m4, $m3, 1
 cmpult $m3, $m0, $m4
 brz $m3, .Lcode1_BB0_16
 # %bb.17: # %if.end6.i82.i
 {
  mov $m3, $m15
  zero $ap3
 }
 {
  sub $m4, $m4, $m0
  f32sub $a3, $azero, $a0
 }
 add $m4, $m4, 5
 setzi $m5, 43691
 sort4x16lo $m6, $m4, $m15
 shr $m4, $m4, 16
 mul $m7, $m6, $m5
 mul $m5, $m4, $m5
 shr $m7, $m7, 16
 add $m5, $m5, $m7
 setzi $m7, 43690
 mul $m6, $m6, $m7
 mul $m4, $m4, $m7
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 add $m6, $m6, $m7
 add $m4, $m4, $m5
 shr $m5, $m6, 16
 shl $m6, $m0, 2
 add $m4, $m4, $m5
 add $m2, $m2, $m6
 shr $m4, $m4, 2
 #APP
 mov $a4, $a3
 {
  rpt $m4, 4
  fnop
 }

 {
  ld32step $a0, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a4:B, $ap0
 }

 {
  nop
  f32v2mul $ap0, $ap0, $ap0
 }

 {
  nop
  f32v2add $ap3, $ap3, $ap0
 }


 #NO_APP
 bri .Lcode1_BB0_18
.Lcode1_BB0_16:
 zero $ap3
.Lcode1_BB0_18: # %_ZL7normSumPKDhS0_jjfb.exit85.i
 shl $m0, $m0, 3
 st64 $ap3, $m0, $m1, 6
 exitz $m15
.Lcode1_BB0_4: # %if.then.i86.i
 shr $m6, $m3, 2
 cmpult $m3, $m0, $m6
 brz $m3, .Lcode1_BB0_21
 # %bb.5: # %if.end.i92.i
 mov $m3, $m15
 {
  sub $m6, $m6, $m0
  f32sub $a0, $azero, $a0
 }
 add $m7, $m6, 5
 st32 $a0, $m11, $m15, 2
 setzi $m8, 43691
 st32 $a1, $m11, $m15, 3
 sort4x16lo $m9, $m7, $m15
 add $m6, $m11, 8
 shr $m7, $m7, 16
 shl $m10, $m0, 3
 add $m0, $m2, $m10
 add $m2, $m5, $m10
 add $m4, $m4, $m10
 add $m1, $m1, $m10
 mul $m5, $m9, $m8
 mul $m8, $m7, $m8
 shr $m5, $m5, 16
 add $m5, $m8, $m5
 setzi $m8, 43690
 mul $m9, $m9, $m8
 mul $m7, $m7, $m8
 sort4x16lo $m8, $m5, $m15
 shr $m5, $m5, 16
 add $m8, $m9, $m8
 add $m5, $m7, $m5
 shr $m7, $m8, 16
 add $m5, $m5, $m7
 shr $m5, $m5, 2
 #APP
 ld32 $a6, $m6, $m15, 0
 ld32 $a7, $m6, $m15, 1
 {
  rpt $m5, 11
  fnop
 }

 {
  ld64step $ap2, $m15, $m0+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f32v2mul $ap1, $a7:B, $ap1
 }

 {
  ld64step $ap2, $m15, $m2+=, 6
  f32v2tof16 $a0, $ap0
 }

 {
  ld64step $ap1, $m15, $m4+=, 6
  f32v2tof16 $a1, $ap1
 }

 {
  nop
  f16v4mul $ap0, $ap0, $ap2
 }

 {
  nop
  f16v4add $ap0, $ap0, $ap1
 }

 {
  st64step $ap0, $m15, $m1+=, 6
  fnop
 }


 #NO_APP
 exitz $m15
.Lcode1_func_end0:
 .size __runCodelet_LayerNormF16, .Lcode1_func_end0-__runCodelet_LayerNormF16
 .section .stack_sizes,"o",@progbits,.text.__runCodelet_LayerNormF16
 .long .Lcode1_func_begin0
 .byte 16
 .section .text.__runCodelet_LayerNormF16,"ax",@progbits
                                        # -- End function
 .ident "clang version 16.0.0 (git@github.com:Software-GCAI/llvm-project.git 6343a843cd5af31429c62a83b6ba249a74d36969)"
 .section ".note.GNU-stack","",@progbits
 .addrsig
# 1280 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .section .text.layer_norm_f16,"ax",@progbits
 .globl layer_norm_f16
 .p2align 2
 .type layer_norm_f16,@function
layer_norm_f16:
 .supervisor
 add $m11, $m11, -128
 st32 $m3, $m11, $m15, 0



 st32 $m4, $m11, $m15, (1 + 0)
 st32 $m5, $m11, $m15, (2 + 0)
 st32 $m2, $m11, $m15, (3 + 0)
 st32 $m6, $m11, $m15, (4 + 0)
 st32 $m7, $m11, $m15, (5 + 0)
 add $m0, $m11, 32
 st32 $m0, $m11, $m15, (6 + 0)





 setzi $m0, __runCodelet_LayerNormF16
.Lwrap1_row:
 setzi $m1, 0
.Lwrap1_stage:
 st32 $m1, $m11, $m15, (7 + 0)
 runall $m0, $m11, 0
 sync (2)
 add $m1, $m1, 1
 cmpeq $m2, $m1, 3
 brz $m2, .Lwrap1_stage
 shl $m2, $m7, 1
 ld32 $m3, $m11, $m15, 0
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 0





 ld32 $m3, $m11, $m15, (3 + 0)
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, (3 + 0)






 sub $m6, $m6, 1
 brnz $m6, .Lwrap1_row
 add $m11, $m11, 128
 br $m10
 .size layer_norm_f16, .-layer_norm_f16
# 1355 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .file "3"
 .section .text.__runCodelet_AddLayerNormF16,"ax",@progbits
 .globl __runCodelet_AddLayerNormF16 # -- Begin function __runCodelet_AddLayerNormF16
 .p2align 2
 .type __runCodelet_AddLayerNormF16,@function
__runCodelet_AddLayerNormF16: # @__runCodelet_AddLayerNormF16
 .worker
.Lcode2_func_begin0:
 # %bb.0: # %entry
 setzi $m6, 16
 cmpult $m6, $m6, __worker_stack_max_growth_plus_one
 brz $m6, _stackoverflow
 add $m11, $m12, -16
 get $m0, 1
 ld32 $m5, $m13, $m15, 8
 and $m0, $m0, 7
 ld32 $m1, $m13, $m15, 7
 ld32 $m3, $m13, $m15, 0
 ld32 $m2, $m13, $m15, 1
 ld32 $m4, $m13, $m15, 6
 brz $m5, .Lcode2_BB0_6
 # %bb.1: # %for.body.preheader.i
 ld64 $ap0, $m1, $m15, 0
 {
  ld64 $ap1, $m1, $m15, 1
  f32v2add $ap0, $ap0, $apzero
 }
 {
  ld64 $ap1, $m1, $m15, 2
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 3
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 4
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 5
  f32v2add $ap0, $ap0, $ap1
 }
 {
  cmpeq $m5, $m5, 1
  f32v2add $ap0, $ap0, $ap1
 }
 {
  st32 $m4, $m11, $m15, 1
  f32add $a0, $a0, $a1
 }
 ld32 $a1, $m11, $m15, 1
 f32fromui32 $a1, $a1
 {
  brz $m5, .Lcode2_BB0_2
  f32div $a0, $a0, $a1
 }
 # %bb.13: # %if.then12.i
 cmpult $m5, $m4, 96
 brnz $m5, .Lcode2_BB0_17
 # %bb.14: # %if.then12.i
 and $m5, $m4, 7
 brnz $m5, .Lcode2_BB0_17
 # %bb.15: # %land.lhs.true1.i74.i
 or $m5, $m2, $m3
 and $m5, $m5, 6
 brz $m5, .Lcode2_BB0_16
.Lcode2_BB0_17: # %if.end.i85.i
 {
  shr $m4, $m4, 1
  zero $ap3
 }
 cmpult $m5, $m0, $m4
 brz $m5, .Lcode2_BB0_19
 # %bb.18: # %if.end6.i92.i
 {
  sub $m4, $m4, $m0
  f32sub $a3, $azero, $a0
 }
 add $m4, $m4, 5
 setzi $m5, 43691
 sort4x16lo $m6, $m4, $m15
 shr $m4, $m4, 16
 mul $m7, $m6, $m5
 mul $m5, $m4, $m5
 shr $m7, $m7, 16
 add $m5, $m5, $m7
 setzi $m7, 43690
 sort4x16lo $m8, $m5, $m15
 mul $m6, $m6, $m7
 shr $m5, $m5, 16
 mul $m4, $m4, $m7
 add $m6, $m6, $m8
 add $m4, $m4, $m5
 shr $m5, $m6, 16
 shl $m6, $m0, 2
 add $m4, $m4, $m5
 add $m3, $m3, $m6
 add $m2, $m2, $m6
 shr $m4, $m4, 2
 #APP
 mov $a4, $a3
 {
  rpt $m4, 6
  fnop
 }

 {
  ld32step $a0, $m15, $m3+=, 6
  fnop
 }

 {
  ld32step $a2, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2add $a0, $a0, $a2
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a4:B, $ap0
 }

 {
  nop
  f32v2mul $ap0, $ap0, $ap0
 }

 {
  nop
  f32v2add $ap3, $ap3, $ap0
 }


 #NO_APP
 bri .Lcode2_BB0_19
.Lcode2_BB0_6: # %if.then.i
 cmpult $m5, $m4, 96
 brnz $m5, .Lcode2_BB0_10
 # %bb.7: # %if.then.i
 and $m5, $m4, 7
 brnz $m5, .Lcode2_BB0_10
 # %bb.8: # %land.lhs.true1.i.i
 or $m5, $m2, $m3
 and $m5, $m5, 6
 brz $m5, .Lcode2_BB0_9
.Lcode2_BB0_10: # %if.end.i.i
 {
  shr $m4, $m4, 1
  zero $ap2
 }
 cmpult $m5, $m0, $m4
 brz $m5, .Lcode2_BB0_12
 # %bb.11: # %if.end6.i.i
 sub $m4, $m4, $m0
 add $m4, $m4, 5
 setzi $m5, 43691
 sort4x16lo $m6, $m4, $m15
 shr $m4, $m4, 16
 mul $m7, $m6, $m5
 mul $m5, $m4, $m5
 shr $m7, $m7, 16
 add $m5, $m5, $m7
 setzi $m7, 43690
 sort4x16lo $m8, $m5, $m15
 mul $m6, $m6, $m7
 shr $m5, $m5, 16
 mul $m4, $m4, $m7
 add $m6, $m6, $m8
 add $m4, $m4, $m5
 shr $m5, $m6, 16
 shl $m6, $m0, 2
 add $m4, $m4, $m5
 add $m3, $m3, $m6
 add $m2, $m2, $m6
 shr $m4, $m4, 2
 #APP
 {
  rpt $m4, 4
  fnop
 }

 {
  ld32step $a0, $m15, $m3+=, 6
  fnop
 }

 {
  ld32step $a2, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2add $a0, $a0, $a2
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap2, $ap2, $ap0
 }


 #NO_APP
.Lcode2_BB0_12: # %_ZL7normSumPKDhS0_jjfb.exit.i
 st64 $ap2, $m1, $m15, $m0
 exitz $m15
.Lcode2_BB0_2: # %for.body21.preheader.i
 {
  ld64 $ap1, $m1, $m15, 6
  setzi $a4, 407485
 }
 {
  and $m7, $m4, 3
  f32v2add $ap1, $ap1, $apzero
 }
 {
  ld32 $m6, $m13, $m15, 2
  or $a4, $a4, 897581056
 }
 ld32 $m5, $m13, $m15, 3
 ld64 $ap3, $m1, $m15, 7
 {
  ld64 $ap3, $m1, $m15, 8
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 9
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 10
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 11
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld32 $m1, $m13, $m15, 4
  f32v2add $ap1, $ap1, $ap3
 }
 f32add $a2, $a2, $a3
 f32div $a1, $a2, $a1
 f32add $a1, $a1, $a4
 #APP
 f32oorx $a1, $a1
 #NO_APP
 brnz $m7, .Lcode2_BB0_20
 # %bb.3: # %land.lhs.true.i.i
 or $m7, $m2, $m3
 or $m7, $m7, $m6
 or $m7, $m7, $m5
 or $m7, $m7, $m1
 and $m7, $m7, 7
 brz $m7, .Lcode2_BB0_4
.Lcode2_BB0_20: # %if.end20.i.i
 shr $m4, $m4, 1
 cmpult $m7, $m0, $m4
 brz $m7, .Lcode2_BB0_22
 # %bb.21: # %if.end24.i.i
 {
  sub $m4, $m4, $m0
  f32sub $a0, $azero, $a0
 }
 add $m7, $m4, 5
 st32 $a0, $m11, $m15, 2
 setzi $m8, 43691
 st32 $a1, $m11, $m15, 3
 sort4x16lo $m9, $m7, $m15
 add $m4, $m11, 8
 shr $m7, $m7, 16
 shl $m10, $m0, 2
 add $m0, $m3, $m10
 add $m2, $m2, $m10
 add $m3, $m6, $m10
 add $m5, $m5, $m10
 add $m1, $m1, $m10
 mul $m6, $m9, $m8
 mul $m8, $m7, $m8
 shr $m6, $m6, 16
 add $m6, $m8, $m6
 setzi $m8, 43690
 mul $m9, $m9, $m8
 mul $m7, $m7, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m8, $m9, $m8
 add $m6, $m7, $m6
 shr $m7, $m8, 16
 add $m6, $m6, $m7
 shr $m6, $m6, 2
 #APP
 ld32 $a6, $m4, $m15, 0
 ld32 $a7, $m4, $m15, 1
 {
  rpt $m6, 11
  fnop
 }

 {
  ld32step $a0, $m15, $m0+=, 6
  fnop
 }

 {
  ld32step $a2, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2add $a0, $a0, $a2
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  ld32step $a2, $m15, $m3+=, 6
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f16v2tof32 $ap1, $a2
 }

 {
  ld32step $a4, $m15, $m5+=, 6
  f32v2mul $ap0, $ap0, $ap1
 }

 {
  nop
  f16v2tof32 $ap1, $a4
 }

 {
  nop
  f32v2add $ap0, $ap0, $ap1
 }

 {
  nop
  f32v2tof16 $a0, $ap0
 }

 {
  st32step $a0, $m15, $m1+=, 6
  fnop
 }


 #NO_APP
.Lcode2_BB0_22: # %_ZN15AddLayerNormF167computeEj.exit
 exitz $m15
.Lcode2_BB0_9: # %if.then.i.i
 shr $m5, $m4, 3
 add $m4, $m11, 8
 sub $m5, $m5, $m0
 add $m5, $m5, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 mul $m8, $m7, $m6
 mul $m6, $m5, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m5, $m5, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m5, $m5, $m6
 shr $m6, $m7, 16
 shl $m7, $m0, 4
 add $m5, $m5, $m6
 add $m3, $m3, $m7
 add $m2, $m2, $m7
 shr $m5, $m5, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 {
  rpt $m5, 5
  fnop
 }

 {
  ld64step $ap0, $m15, $m3+=, 1
  fnop
 }

 {
  ld64step $ap1, $m15, $m3+=, 11
  fnop
 }

 {
  ld64step $ap2, $m15, $m2+=, 1
  fnop
 }

 {
  ld64step $ap3, $m15, $m2+=, 11
  f16v4add $ap0, $ap0, $ap2
 }

 {
  nop
  f16v4add $ap1, $ap1, $ap3
 }

 {
  nop
  f16v8acc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m4, $m15, 0

 #NO_APP
 ld64 $ap2, $m11, $m15, 1
 st64 $ap2, $m1, $m15, $m0
 exitz $m15
.Lcode2_BB0_16: # %if.then.i82.i
 {
  shr $m4, $m4, 2
  f32sub $a7, $azero, $a0
 }
 sub $m5, $m4, $m0
 add $m4, $m11, 8
 add $m5, $m5, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 mul $m8, $m7, $m6
 mul $m6, $m5, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m5, $m5, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m5, $m5, $m6
 shr $m6, $m7, 16
 shl $m7, $m0, 3
 add $m5, $m5, $m6
 add $m3, $m3, $m7
 add $m2, $m2, $m7
 shr $m5, $m5, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 mov $a6, $a7
 {
  rpt $m5, 7
  fnop
 }

 {
  ld64step $ap2, $m15, $m3+=, 6
  fnop
 }

 {
  ld64step $ap0, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v4add $ap2, $ap2, $ap0
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v4sqacc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m4, $m15, 0

 #NO_APP
 ld64 $ap3, $m11, $m15, 1
.Lcode2_BB0_19: # %_ZL7normSumPKDhS0_jjfb.exit95.i
 shl $m0, $m0, 3
 st64 $ap3, $m0, $m1, 6
 exitz $m15
.Lcode2_BB0_4: # %if.then.i100.i
 shr $m4, $m4, 2
 cmpult $m7, $m0, $m4
 brz $m7, .Lcode2_BB0_22
 # %bb.5: # %if.end.i106.i
 {
  sub $m4, $m4, $m0
  f32sub $a0, $azero, $a0
 }
 add $m7, $m4, 5
 st32 $a0, $m11, $m15, 2
 setzi $m8, 43691
 st32 $a1, $m11, $m15, 3
 sort4x16lo $m9, $m7, $m15
 add $m4, $m11, 8
 shr $m7, $m7, 16
 shl $m10, $m0, 3
 add $m0, $m3, $m10
 add $m2, $m2, $m10
 add $m3, $m6, $m10
 add $m5, $m5, $m10
 add $m1, $m1, $m10
 mul $m6, $m9, $m8
 mul $m8, $m7, $m8
 shr $m6, $m6, 16
 add $m6, $m8, $m6
 setzi $m8, 43690
 mul $m9, $m9, $m8
 mul $m7, $m7, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m8, $m9, $m8
 add $m6, $m7, $m6
 shr $m7, $m8, 16
 add $m6, $m6, $m7
 shr $m6, $m6, 2
 #APP
 ld32 $a6, $m4, $m15, 0
 ld32 $a7, $m4, $m15, 1
 {
  rpt $m6, 13
  fnop
 }

 {
  ld64step $ap2, $m15, $m0+=, 6
  fnop
 }

 {
  ld64step $ap0, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v4add $ap2, $ap2, $ap0
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f32v2mul $ap1, $a7:B, $ap1
 }

 {
  ld64step $ap2, $m15, $m3+=, 6
  f32v2tof16 $a0, $ap0
 }

 {
  ld64step $ap1, $m15, $m5+=, 6
  f32v2tof16 $a1, $ap1
 }

 {
  nop
  f16v4mul $ap0, $ap0, $ap2
 }

 {
  nop
  f16v4add $ap0, $ap0, $ap1
 }

 {
  st64step $ap0, $m15, $m1+=, 6
  fnop
 }


 #NO_APP
 exitz $m15
.Lcode2_func_end0:
 .size __runCodelet_AddLayerNormF16, .Lcode2_func_end0-__runCodelet_AddLayerNormF16
 .section .stack_sizes,"o",@progbits,.text.__runCodelet_AddLayerNormF16
 .long .Lcode2_func_begin0
 .byte 16
 .section .text.__runCodelet_AddLayerNormF16,"ax",@progbits
                                        # -- End function
 .ident "clang version 16.0.0 (git@github.com:Software-GCAI/llvm-project.git 6343a843cd5af31429c62a83b6ba249a74d36969)"
 .section ".note.GNU-stack","",@progbits
 .addrsig
# 2064 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .section .text.add_layer_norm_f16,"ax",@progbits
 .globl add_layer_norm_f16
 .p2align 2
 .type add_layer_norm_f16,@function
add_layer_norm_f16:
 .supervisor
 add $m11, $m11, -160
 st32 $m3, $m11, $m15, 0

 st32 $m4, $m11, $m15, 1

 st32 $m5, $m11, $m15, (1 + 1)
 st32 $m6, $m11, $m15, (2 + 1)
 st32 $m2, $m11, $m15, (3 + 1)
 st32 $m7, $m11, $m15, (4 + 1)
 st32 $m8, $m11, $m15, (5 + 1)
 add $m0, $m11, 64
 st32 $m0, $m11, $m15, (6 + 1)





 setzi $m0, __runCodelet_AddLayerNormF16
.Lwrap2_row:
 setzi $m1, 0
.Lwrap2_stage:
 st32 $m1, $m11, $m15, (7 + 1)
 runall $m0, $m11, 0
 sync (2)
 add $m1, $m1, 1
 cmpeq $m2, $m1, 3
 brz $m2, .Lwrap2_stage
 shl $m2, $m8, 1
 ld32 $m3, $m11, $m15, 0
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 0





 ld32 $m3, $m11, $m15, (3 + 1)
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, (3 + 1)


 ld32 $m3, $m11, $m15, 1
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 1

 sub $m7, $m7, 1
 brnz $m7, .Lwrap2_row
 add $m11, $m11, 160
 br $m10
 .size add_layer_norm_f16, .-add_layer_norm_f16
# 2139 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .file "3"
 .section .text.__runCodelet_LayerNormMoments,"ax",@progbits
 .globl __runCodelet_LayerNormMoments # -- Begin function __runCodelet_LayerNormMoments
 .p2align 2
 .type __runCodelet_LayerNormMoments,@function
__runCodelet_LayerNormMoments: # @__runCodelet_LayerNormMoments
 .worker
.Lcode3_func_begin0:
 # %bb.0: # %entry
 setzi $m6, 16
 cmpult $m6, $m6, __worker_stack_max_growth_plus_one
 brz $m6, _stackoverflow
 add $m11, $m12, -16
 get $m0, 1
 ld32 $m2, $m13, $m15, 4
 and $m1, $m0, 7
 ld32 $m0, $m13, $m15, 3
 ld32 $m3, $m13, $m15, 0
 ld32 $m4, $m13, $m15, 2
 brz $m2, .Lcode3_BB0_5
 # %bb.1: # %for.body.preheader.i
 ld64 $ap0, $m0, $m15, 0
 {
  ld64 $ap1, $m0, $m15, 1
  f32v2add $ap0, $ap0, $apzero
 }
 {
  ld64 $ap1, $m0, $m15, 2
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m0, $m15, 3
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m0, $m15, 4
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m0, $m15, 5
  f32v2add $ap0, $ap0, $ap1
 }
 {
  cmpeq $m2, $m2, 1
  f32v2add $ap0, $ap0, $ap1
 }
 {
  st32 $m4, $m11, $m15, 1
  f32add $a0, $a0, $a1
 }
 ld32 $a1, $m11, $m15, 1
 f32fromui32 $a1, $a1
 {
  brz $m2, .Lcode3_BB0_15
  f32div $a0, $a0, $a1
 }
 # %bb.2: # %if.then11.i
 cmpult $m5, $m4, 96
 shl $m2, $m1, 3
 brnz $m5, .Lcode3_BB0_12
 # %bb.3: # %if.then11.i
 or $m5, $m4, $m3
 and $m5, $m5, 7
 brnz $m5, .Lcode3_BB0_12
 # %bb.4: # %if.then.i63.i
 mov $m5, $m15
 {
  shr $m4, $m4, 2
  f32sub $a7, $azero, $a0
 }
 sub $m4, $m4, $m1
 add $m1, $m11, 8
 add $m4, $m4, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m4, $m15
 shr $m4, $m4, 16
 add $m3, $m3, $m2
 mul $m8, $m7, $m6
 mul $m6, $m4, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m4, $m4, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m4, $m4, $m6
 shr $m6, $m7, 16
 add $m4, $m4, $m6
 shr $m4, $m4, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 mov $a6, $a7
 {
  rpt $m4, 5
  fnop
 }

 {
  ld64step $ap2, $m15, $m3+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v4sqacc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m1, $m15, 0

 #NO_APP
 ld64 $ap3, $m11, $m15, 1
 st64 $ap3, $m2, $m0, 6
 exitz $m15
.Lcode3_BB0_5: # %if.then.i
 cmpult $m2, $m4, 96
 brnz $m2, .Lcode3_BB0_8
 # %bb.6: # %if.then.i
 or $m2, $m4, $m3
 and $m2, $m2, 7
 brnz $m2, .Lcode3_BB0_8
 # %bb.7: # %if.then.i.i
 mov $m2, $m15
 shr $m5, $m4, 3
 add $m4, $m11, 8
 sub $m5, $m5, $m1
 add $m5, $m5, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 mul $m8, $m7, $m6
 mul $m6, $m5, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m5, $m5, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m5, $m5, $m6
 shr $m6, $m7, 16
 shl $m7, $m1, 4
 add $m5, $m5, $m6
 add $m3, $m3, $m7
 shr $m5, $m5, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 {
  rpt $m5, 2
  fnop
 }

 {
  ld64step $ap0, $m15, $m3+=, 1
  fnop
 }

 {
  ld64step $ap1, $m15, $m3+=, 11
  fnop
 }

 {
  nop
  f16v8acc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m4, $m15, 0

 #NO_APP
 ld64 $ap2, $m11, $m15, 1
 st64 $ap2, $m0, $m15, $m1
 exitz $m15
.Lcode3_BB0_15: # %if.else.i
 brz $m1, .Lcode3_BB0_16
 # %bb.17: # %_ZN16LayerNormMoments7computeEj.exit
 exitz $m15
.Lcode3_BB0_8: # %if.end.i.i
 shr $m4, $m4, 1
 cmpult $m2, $m1, $m4
 brz $m2, .Lcode3_BB0_9
 # %bb.10: # %if.end6.i.i
 {
  mov $m2, $m15
  zero $ap2
 }
 sub $m4, $m4, $m1
 add $m4, $m4, 5
 setzi $m5, 43691
 sort4x16lo $m6, $m4, $m15
 shr $m4, $m4, 16
 mul $m7, $m6, $m5
 mul $m5, $m4, $m5
 shr $m7, $m7, 16
 add $m5, $m5, $m7
 setzi $m7, 43690
 mul $m6, $m6, $m7
 mul $m4, $m4, $m7
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 add $m6, $m6, $m7
 add $m4, $m4, $m5
 shr $m5, $m6, 16
 shl $m6, $m1, 2
 add $m4, $m4, $m5
 add $m3, $m3, $m6
 shr $m4, $m4, 2
 #APP
 {
  rpt $m4, 2
  fnop
 }

 {
  ld32step $a0, $m15, $m3+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap2, $ap2, $ap0
 }


 #NO_APP
 st64 $ap2, $m0, $m15, $m1
 exitz $m15
.Lcode3_BB0_12: # %if.end.i66.i
 {
  shr $m5, $m4, 1
  zero $ap3
 }
 cmpult $m4, $m1, $m5
 brz $m4, .Lcode3_BB0_14
 # %bb.13: # %if.end6.i72.i
 mov $m4, $m15
 {
  sub $m5, $m5, $m1
  f32sub $a3, $azero, $a0
 }
 add $m5, $m5, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 shl $m1, $m1, 2
 add $m1, $m3, $m1
 mul $m3, $m7, $m6
 mul $m6, $m5, $m6
 shr $m3, $m3, 16
 add $m3, $m6, $m3
 setzi $m6, 43690
 mul $m7, $m7, $m6
 mul $m5, $m5, $m6
 sort4x16lo $m6, $m3, $m15
 shr $m3, $m3, 16
 add $m6, $m7, $m6
 add $m3, $m5, $m3
 shr $m5, $m6, 16
 add $m3, $m3, $m5
 shr $m3, $m3, 2
 #APP
 mov $a4, $a3
 {
  rpt $m3, 4
  fnop
 }

 {
  ld32step $a0, $m15, $m1+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a4:B, $ap0
 }

 {
  nop
  f32v2mul $ap0, $ap0, $ap0
 }

 {
  nop
  f32v2add $ap3, $ap3, $ap0
 }


 #NO_APP
.Lcode3_BB0_14: # %_ZL7normSumPKDhS0_jjfb.exit75.i
 st64 $ap3, $m2, $m0, 6
 exitz $m15
.Lcode3_BB0_16: # %for.body21.preheader.i
 ld64 $ap1, $m0, $m15, 6
 {
  ld64 $ap2, $m0, $m15, 7
  f32v2add $ap1, $ap1, $apzero
 }
 {
  ld64 $ap2, $m0, $m15, 8
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld64 $ap2, $m0, $m15, 9
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld64 $ap2, $m0, $m15, 10
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld64 $ap2, $m0, $m15, 11
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld32 $m0, $m13, $m15, 1
  f32v2add $ap1, $ap1, $ap2
 }
 f32add $a1, $a2, $a3
 st64 $ap0, $m0, $m15, 0
 exitz $m15
.Lcode3_BB0_9:
 zero $ap2
 st64 $ap2, $m0, $m15, $m1
 exitz $m15
.Lcode3_func_end0:
 .size __runCodelet_LayerNormMoments, .Lcode3_func_end0-__runCodelet_LayerNormMoments
 .section .stack_sizes,"o",@progbits,.text.__runCodelet_LayerNormMoments
 .long .Lcode3_func_begin0
 .byte 16
 .section .text.__runCodelet_LayerNormMoments,"ax",@progbits
                                        # -- End function
 .ident "clang version 16.0.0 (git@github.com:Software-GCAI/llvm-project.git 6343a843cd5af31429c62a83b6ba249a74d36969)"
 .section ".note.GNU-stack","",@progbits
 .addrsig
# 2534 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .section .text.layer_norm_moments,"ax",@progbits
 .globl layer_norm_moments
 .p2align 2
 .type layer_norm_moments,@function
layer_norm_moments:
 .supervisor
 add $m11, $m11, -128
 st32 $m3, $m11, $m15, 0
 st32 $m2, $m11, $m15, 1
 st32 $m5, $m11, $m15, 2
 add $m0, $m11, 32
 st32 $m0, $m11, $m15, 3




 setzi $m0, __runCodelet_LayerNormMoments
.Lwrap3_row:
 setzi $m1, 0
.Lwrap3_stage:
 st32 $m1, $m11, $m15, 4
 runall $m0, $m11, 0
 sync (2)
 add $m1, $m1, 1
 cmpeq $m2, $m1, 3
 brz $m2, .Lwrap3_stage
 ld32 $m3, $m11, $m15, 0
 shl $m2, $m5, 1
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 0
# 2574 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 ld32 $m2, $m11, $m15, 1
 add $m2, $m2, 8
 st32 $m2, $m11, $m15, 1
 sub $m4, $m4, 1
 brnz $m4, .Lwrap3_row
 add $m11, $m11, 128
 br $m10
 .size layer_norm_moments, .-layer_norm_moments
# 2599 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .file "3"
 .section .text.__runCodelet_LayerNormApply,"ax",@progbits
 .globl __runCodelet_LayerNormApply # -- Begin function __runCodelet_LayerNormApply
 .p2align 2
 .type __runCodelet_LayerNormApply,@function
__runCodelet_LayerNormApply: # @__runCodelet_LayerNormApply
 .worker
.Lcode4_func_begin0:
 # %bb.0: # %entry
 setzi $m6, 128
 cmpult $m6, $m6, __worker_stack_max_growth_plus_one
 brz $m6, _stackoverflow
 add $m11, $m12, -128
 get $m2, 1
 ld32 $m0, $m13, $m15, 5
 brz $m0, .Lcode4_BB0_19
 # %bb.1: # %for.cond9.preheader.lr.ph.i
 mov $m1, $m15
 and $m3, $m2, 7
 {
  add $m0, $m0, -1
  setzi $a0, 407485
 }
 ld32 $m2, $m13, $m15, 6
 st32 $m2, $m11, $m15, 1
 ld32 $a1, $m11, $m15, 1
 {
  shr $m5, $m2, 1
  f32fromui32 $a5, $a1
 }
 {
  sub $m4, 5, $m3
  or $a6, $a0, 897581056
 }
 shr $m6, $m2, 2
 st32 $m5, $m11, $m15, 23 # 4-byte Folded Spill
 add $m5, $m5, $m4
 st32 $m6, $m11, $m15, 11 # 4-byte Folded Spill
 add $m4, $m6, $m4
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 sort4x16lo $m8, $m4, $m15
 shr $m4, $m4, 16
 mul $m9, $m7, $m6
 shr $m9, $m9, 16
 st32 $m9, $m11, $m15, 29 # 4-byte Folded Spill
 mul $m10, $m8, $m6
 shr $m9, $m10, 16
 st32 $m9, $m11, $m15, 28 # 4-byte Folded Spill
 mul $m9, $m5, $m6
 ld32 $m10, $m11, $m15, 29 # 4-byte Folded Reload
 add $m9, $m9, $m10
 mul $m6, $m4, $m6
 ld32 $m10, $m11, $m15, 28 # 4-byte Folded Reload
 add $m6, $m6, $m10
 setzi $m10, 43690
 mul $m7, $m7, $m10
 mul $m8, $m8, $m10
 mul $m5, $m5, $m10
 mul $m4, $m4, $m10
 sort4x16lo $m10, $m9, $m15
 add $m7, $m7, $m10
 shr $m9, $m9, 16
 add $m5, $m5, $m9
 sort4x16lo $m9, $m6, $m15
 shr $m10, $m6, 16
 add $m8, $m8, $m9
 ld32 $m6, $m13, $m15, 7
 shr $m7, $m7, 16
 add $m4, $m4, $m10
 shr $m8, $m8, 16
 ld32 $m9, $m13, $m15, 1
 st32 $m6, $m11, $m15, 1
 ld32 $a0, $m11, $m15, 1
 {
  add $m5, $m5, $m7
  f32fromui32 $a0, $a0
 }
 ld32 $m10, $m13, $m15, 2
 {
  st32 $a0, $m11, $m15, 21
  f32div $a0, $azero, $a0
 }
 st32 $a0, $m11, $m15, 13 # 4-byte Folded Spill
 add $m4, $m4, $m8
 ld32 $m7, $m13, $m15, 3
 st32 $m7, $m11, $m15, 29 # 4-byte Folded Spill
 shr $m5, $m5, 2
 st32 $m5, $m11, $m15, 17 # 4-byte Folded Spill
 shr $m4, $m4, 2
 st32 $m4, $m11, $m15, 5 # 4-byte Folded Spill
 mul $m4, $m6, $m2
 st32 $m4, $m11, $m15, 1
 ld32 $a0, $m11, $m15, 1
 {
  shl $m4, $m3, 1
  f32fromui32 $a7, $a0
 }
 shl $m4, $m4, 1
 st32 $m4, $m11, $m15, 16 # 4-byte Folded Spill
 shl $m5, $m3, 2
 shl $m4, $m3, 3
 ld32 $m7, $m13, $m15, 0
 st32 $m7, $m11, $m15, 24 # 4-byte Folded Spill
 ld32 $m8, $m13, $m15, 4
 st32 $m8, $m11, $m15, 27 # 4-byte Folded Spill
 st32 $m2, $m11, $m15, 28 # 4-byte Folded Spill
 and $m2, $m2, 3
 st32 $m2, $m11, $m15, 26 # 4-byte Folded Spill
 or $m2, $m10, $m9
 st32 $m2, $m11, $m15, 12 # 4-byte Folded Spill
 add $m2, $m9, $m5
 st32 $m2, $m11, $m15, 15 # 4-byte Folded Spill
 add $m2, $m9, $m4
 st32 $m2, $m11, $m15, 3 # 4-byte Folded Spill
 add $m2, $m10, $m4
 st32 $m2, $m11, $m15, 2 # 4-byte Folded Spill
 ld32 $m4, $m11, $m15, 29 # 4-byte Folded Reload
 st32 $m5, $m11, $m15, 4 # 4-byte Folded Spill
 add $m2, $m10, $m5
 st32 $m2, $m11, $m15, 14 # 4-byte Folded Spill
 shl $m2, $m6, 3
 st32 $m2, $m11, $m15, 25 # 4-byte Folded Spill
 add $m10, $m4, 4
 st32 $m3, $m11, $m15, 20 # 4-byte Folded Spill
 st32 $a6, $m11, $m15, 19 # 4-byte Folded Spill
 st32 $a7, $m11, $m15, 18 # 4-byte Folded Spill
 st32 $a5, $m11, $m15, 6 # 4-byte Folded Spill
.Lcode4_BB0_2: # %for.cond9.preheader.i
                                        # =>This Loop Header: Depth=1
                                        # Child Loop BB0_10 Depth 2
                                        # Child Loop BB0_13 Depth 2
 brz $m6, .Lcode4_BB0_3
 # %bb.8: # %for.body12.lr.ph.i
                                        # in Loop: Header=BB0_2 Depth=1
 {
  setzi $m9, 1
  mov $a0, $azero
 }
 mov $m5, $m4
 cmpslt $m8, $m9, $m6
 ld32step $a1, $m15, $m5+=, 2
 add $m9, $m6, -1
 brz $m8, .Lcode4_BB0_11
 # %bb.9: # %for.body12.i
                                        # in Loop: Header=BB0_2 Depth=1
 add $m9, $m9, -1
.Lcode4_BB0_10: # %for.body12.i
                                        # Parent Loop BB0_2 Depth=1
                                        # => This Inner Loop Header: Depth=2
 {
  ld32step $a1, $m15, $m5+=, 2
  f32add $a0, $a0, $a1
 }
 brnzdec $m9, .Lcode4_BB0_10
.Lcode4_BB0_11: # in Loop: Header=BB0_2 Depth=1
 f32add $a0, $a0, $a1
 {
  ld32 $a2, $m11, $m15, 21
  mov $a1, $azero
 }
 {
  add $m2, $m15, -4
  f32div $a0, $a0, $a2
 }
 ld64 $ap1, $m10, $m2, 0
 {
  setzi $m2, 1
  f32sub $a2, $a2, $a0
 }
 {
  cmpslt $m2, $m2, $m6
  f32mul $a4, $a2, $a5
 }
 {
  add $m9, $m10, 8
  f32mul $a2, $a4, $a2
 }
 add $m5, $m6, -1
 brz $m2, .Lcode4_BB0_14
 # %bb.12: # %for.body18.i
                                        # in Loop: Header=BB0_2 Depth=1
 add $m5, $m5, -1
.Lcode4_BB0_13: # %for.body18.i
                                        # Parent Loop BB0_2 Depth=1
                                        # => This Inner Loop Header: Depth=2
 {
  add $m2, $m15, -4
  f32add $a4, $a2, $a3
 }
 ld64 $ap1, $m9, $m2, 0
 {
  add $m9, $m9, 8
  f32sub $a2, $a2, $a0
 }
 f32add $a1, $a1, $a4
 f32mul $a4, $a2, $a5
 {
  brnzdec $m5, .Lcode4_BB0_13
  f32mul $a2, $a4, $a2
 }
.Lcode4_BB0_14: # in Loop: Header=BB0_2 Depth=1
 f32add $a2, $a2, $a3
 {
  bri .Lcode4_BB0_4
  f32add $a1, $a1, $a2
 }
.Lcode4_BB0_3: # in Loop: Header=BB0_2 Depth=1
 {
  ld32 $a0, $m11, $m15, 13
  mov $a1, $azero
 }
.Lcode4_BB0_4: # %for.cond.cleanup17.i
                                        # in Loop: Header=BB0_2 Depth=1
 {
  ld32 $m2, $m11, $m15, 28
  f32div $a1, $a1, $a7
 }
 {
  mul $m5, $m1, $m2
  f32add $a1, $a1, $a6
 }
 shl $m5, $m5, 1
 #APP
 f32oorx $a1, $a1
 #NO_APP
 ld32 $m2, $m11, $m15, 24 # 4-byte Folded Reload
 add $m9, $m2, $m5
 ld32 $m2, $m11, $m15, 27 # 4-byte Folded Reload
 add $m5, $m2, $m5
 ld32 $m2, $m11, $m15, 26 # 4-byte Folded Reload
 brnz $m2, .Lcode4_BB0_15
 # %bb.5: # %land.lhs.true.i.i
                                        # in Loop: Header=BB0_2 Depth=1
 ld32 $m2, $m11, $m15, 12 # 4-byte Folded Reload
 or $m8, $m2, $m9
 or $m8, $m8, $m5
 and $m8, $m8, 6
 brz $m8, .Lcode4_BB0_6
.Lcode4_BB0_15: # %if.end18.i.i
                                        # in Loop: Header=BB0_2 Depth=1
 ld32 $m2, $m11, $m15, 23 # 4-byte Folded Reload
 cmpult $m2, $m3, $m2
 brz $m2, .Lcode4_BB0_18
 # %bb.16: # %if.end22.i.i
                                        # in Loop: Header=BB0_2 Depth=1
 {
  mov $m2, $m15
  f32sub $a0, $azero, $a0
 }
 st32 $m4, $m11, $m15, 29 # 4-byte Folded Spill
 ld32 $m4, $m11, $m15, 16 # 4-byte Folded Reload
 add $m3, $m9, $m4
 add $m5, $m5, $m4
 st32 $a0, $m11, $m15, 30
 st32 $a1, $m11, $m15, 31
 add $m4, $m11, 120
 st32 $m4, $m11, $m15, 22 # 4-byte Folded Spill
 ld32 $m9, $m11, $m15, 14 # 4-byte Folded Reload
 ld32 $m4, $m11, $m15, 15 # 4-byte Folded Reload
 mov $m7, $m0
 mov $m0, $m1
 mov $m1, $m6
 ld32 $m6, $m11, $m15, 17 # 4-byte Folded Reload
 ld32 $m8, $m11, $m15, 22 # 4-byte Folded Reload
 #APP
 ld32 $a6, $m8, $m15, 0
 ld32 $a7, $m8, $m15, 1
 {
  rpt $m6, 9
  fnop
 }

 {
  ld32step $a0, $m15, $m3+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  ld32step $a2, $m15, $m4+=, 6
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f16v2tof32 $ap1, $a2
 }

 {
  ld32step $a4, $m15, $m9+=, 6
  f32v2mul $ap0, $ap0, $ap1
 }

 {
  nop
  f16v2tof32 $ap1, $a4
 }

 {
  nop
  f32v2add $ap0, $ap0, $ap1
 }

 {
  nop
  f32v2tof16 $a0, $ap0
 }

 {
  st32step $a0, $m15, $m5+=, 6
  fnop
 }


 #NO_APP
 ld32 $m4, $m11, $m15, 29 # 4-byte Folded Reload
 ld32 $a7, $m11, $m15, 18 # 4-byte Folded Reload
 mov $m6, $m1
 mov $m1, $m0
 mov $m0, $m7
 ld32 $a6, $m11, $m15, 19 # 4-byte Folded Reload
.Lcode4_BB0_17: # %_ZL9normApplyPKDhS0_S0_S0_PDhjjff.exit.i
                                        # in Loop: Header=BB0_2 Depth=1
 ld32 $m3, $m11, $m15, 20 # 4-byte Folded Reload
.Lcode4_BB0_18: # %_ZL9normApplyPKDhS0_S0_S0_PDhjjff.exit.i
                                        # in Loop: Header=BB0_2 Depth=1
 add $m1, $m1, 1
 ld32 $m2, $m11, $m15, 25 # 4-byte Folded Reload
 add $m4, $m4, $m2
 add $m10, $m10, $m2
 brnzdec $m0, .Lcode4_BB0_2
 bri .Lcode4_BB0_19
.Lcode4_BB0_6: # %if.then.i.i
                                        # in Loop: Header=BB0_2 Depth=1
 ld32 $m2, $m11, $m15, 11 # 4-byte Folded Reload
 cmpult $m8, $m3, $m2
 brz $m8, .Lcode4_BB0_18
 # %bb.7: # %if.end.i.i
                                        # in Loop: Header=BB0_2 Depth=1
 st32 $m15, $m11, $m15, 10 # 4-byte Folded Spill
 ld32 $m2, $m11, $m15, 4 # 4-byte Folded Reload
 {
  shl $m2, $m2, 1
  f32sub $a0, $azero, $a0
 }
 add $m3, $m9, $m2
 st32 $m3, $m11, $m15, 9 # 4-byte Folded Spill
 st32 $a0, $m11, $m15, 30
 add $m2, $m5, $m2
 st32 $m2, $m11, $m15, 8 # 4-byte Folded Spill
 st32 $a1, $m11, $m15, 31
 add $m3, $m11, 120
 st32 $m3, $m11, $m15, 22 # 4-byte Folded Spill
 ld32 $m2, $m11, $m15, 2 # 4-byte Folded Reload
 st32 $m2, $m11, $m15, 7 # 4-byte Folded Spill
 ld32 $m5, $m11, $m15, 3 # 4-byte Folded Reload
 st32 $m4, $m11, $m15, 29 # 4-byte Folded Spill
 ld32 $m4, $m11, $m15, 5 # 4-byte Folded Reload
 ld32 $m8, $m11, $m15, 22 # 4-byte Folded Reload
 ld32 $m9, $m11, $m15, 10 # 4-byte Folded Reload
 ld32 $m2, $m11, $m15, 9 # 4-byte Folded Reload
 ld32 $m3, $m11, $m15, 8 # 4-byte Folded Reload
 ld32 $m7, $m11, $m15, 7 # 4-byte Folded Reload
 #APP
 ld32 $a6, $m8, $m15, 0
 ld32 $a7, $m8, $m15, 1
 {
  rpt $m4, 11
  fnop
 }

 {
  ld64step $ap2, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f32v2mul $ap1, $a7:B, $ap1
 }

 {
  ld64step $ap2, $m15, $m5+=, 6
  f32v2tof16 $a0, $ap0
 }

 {
  ld64step $ap1, $m15, $m7+=, 6
  f32v2tof16 $a1, $ap1
 }

 {
  nop
  f16v4mul $ap0, $ap0, $ap2
 }

 {
  nop
  f16v4add $ap0, $ap0, $ap1
 }

 {
  st64step $ap0, $m15, $m3+=, 6
  fnop
 }


 #NO_APP
 ld32 $m4, $m11, $m15, 29 # 4-byte Folded Reload
 ld32 $a7, $m11, $m15, 18 # 4-byte Folded Reload
 ld32 $a6, $m11, $m15, 19 # 4-byte Folded Reload
 ld32 $a5, $m11, $m15, 6 # 4-byte Folded Reload
 bri .Lcode4_BB0_17
.Lcode4_BB0_19: # %_ZN14LayerNormApply7computeEj.exit
 exitz $m15
.Lcode4_func_end0:
 .size __runCodelet_LayerNormApply, .Lcode4_func_end0-__runCodelet_LayerNormApply
 .section .stack_sizes,"o",@progbits,.text.__runCodelet_LayerNormApply
 .long .Lcode4_func_begin0
 .ascii "\200\001"
 .section .text.__runCodelet_LayerNormApply,"ax",@progbits
                                        # -- End function
 .ident "clang version 16.0.0 (git@github.com:Software-GCAI/llvm-project.git 6343a843cd5af31429c62a83b6ba249a74d36969)"
 .section ".note.GNU-stack","",@progbits
 .addrsig





# 1 "/srv/home/gc-sdk/ipu-stack/device/worker_call.S" 1




 .text
 .allow_optimizations
 .set SYNC_COMPUTE_SET, (2)

 .section .text.layer_norm_apply,"ax",@progbits
 .globl layer_norm_apply
 .p2align 2
 .type layer_norm_apply,@function
layer_norm_apply:
 .supervisor
 add $m11, $m11, -48
 .set argument_index, 0
 .irp argument, $m3,$m4,$m5,$m6,$m2,$m7,$m8,$m9
 st32 \argument, $m11, $m15, argument_index
 .set argument_index, argument_index + 1
 .endr



 setzi $m0, __runCodelet_LayerNormApply

1:
 runall $m0, $m11, 0
 sync SYNC_COMPUTE_SET



 add $m11, $m11, 48
 br $m10
 .size layer_norm_apply, .-layer_norm_apply
# 3068 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S" 2




 .text
 .allow_optimizations
 .file "3"
 .section .text.__runCodelet_LayerNormF8,"ax",@progbits
 .globl __runCodelet_LayerNormF8 # -- Begin function __runCodelet_LayerNormF8
 .p2align 2
 .type __runCodelet_LayerNormF8,@function
__runCodelet_LayerNormF8: # @__runCodelet_LayerNormF8
 .worker
.Lcode5_func_begin0:
 # %bb.0: # %entry
 setzi $m6, 40
 cmpult $m6, $m6, __worker_stack_max_growth_plus_one
 brz $m6, _stackoverflow
 add $m11, $m12, -40
 get $m0, 1
 ld32 $m3, $m13, $m15, 7
 and $m0, $m0, 7
 ld32 $m1, $m13, $m15, 6
 ld32 $m5, $m13, $m15, 0
 ld32 $m2, $m13, $m15, 5
 brz $m3, .Lcode5_BB0_6
 # %bb.1: # %for.body.preheader.i
 ld64 $ap0, $m1, $m15, 0
 {
  ld64 $ap1, $m1, $m15, 1
  f32v2add $ap0, $ap0, $apzero
 }
 {
  ld64 $ap1, $m1, $m15, 2
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 3
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 4
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m1, $m15, 5
  f32v2add $ap0, $ap0, $ap1
 }
 {
  cmpeq $m3, $m3, 1
  f32v2add $ap0, $ap0, $ap1
 }
 {
  st32 $m2, $m11, $m15, 0
  f32add $a0, $a0, $a1
 }
 ld32 $a1, $m11, $m15, 0
 f32fromui32 $a1, $a1
 {
  brz $m3, .Lcode5_BB0_2
  f32div $a0, $a0, $a1
 }
 # %bb.13: # %if.then11.i
 cmpult $m3, $m2, 96
 brnz $m3, .Lcode5_BB0_16
 # %bb.14: # %if.then11.i
 or $m3, $m2, $m5
 and $m3, $m3, 7
 brnz $m3, .Lcode5_BB0_16
 # %bb.15: # %if.then.i75.i
 mov $m3, $m15
 {
  shr $m2, $m2, 2
  f32sub $a7, $azero, $a0
 }
 sub $m4, $m2, $m0
 add $m2, $m11, 32
 add $m4, $m4, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m4, $m15
 shr $m4, $m4, 16
 mul $m8, $m7, $m6
 mul $m6, $m4, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m4, $m4, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m4, $m4, $m6
 shr $m6, $m7, 16
 shl $m7, $m0, 3
 add $m4, $m4, $m6
 add $m5, $m5, $m7
 shr $m4, $m4, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 mov $a6, $a7
 {
  rpt $m4, 5
  fnop
 }

 {
  ld64step $ap2, $m15, $m5+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v4sqacc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m2, $m15, 0

 #NO_APP
 ld64 $ap3, $m11, $m15, 4
 bri .Lcode5_BB0_18
.Lcode5_BB0_6: # %if.then.i
 cmpult $m3, $m2, 96
 brnz $m3, .Lcode5_BB0_9
 # %bb.7: # %if.then.i
 or $m3, $m2, $m5
 and $m3, $m3, 7
 brnz $m3, .Lcode5_BB0_9
 # %bb.8: # %if.then.i.i
 mov $m3, $m15
 shr $m4, $m2, 3
 add $m2, $m11, 32
 sub $m4, $m4, $m0
 add $m4, $m4, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m4, $m15
 shr $m4, $m4, 16
 mul $m8, $m7, $m6
 mul $m6, $m4, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m4, $m4, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m4, $m4, $m6
 shr $m6, $m7, 16
 shl $m7, $m0, 4
 add $m4, $m4, $m6
 add $m5, $m5, $m7
 shr $m4, $m4, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 {
  rpt $m4, 2
  fnop
 }

 {
  ld64step $ap0, $m15, $m5+=, 1
  fnop
 }

 {
  ld64step $ap1, $m15, $m5+=, 11
  fnop
 }

 {
  nop
  f16v8acc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m2, $m15, 0

 #NO_APP
 ld64 $ap2, $m11, $m15, 4
 st64 $ap2, $m1, $m15, $m0
 exitz $m15
.Lcode5_BB0_2: # %for.body20.preheader.i
 {
  ld64 $ap1, $m1, $m15, 6
  setzi $a4, 407485
 }
 {
  ld32 $m3, $m13, $m15, 9
  f32v2add $ap1, $ap1, $apzero
 }
 {
  sub $m3, 0, $m3
  or $a4, $a4, 897581056
 }
 {
  and $m3, $m3, 255
  setzi $a5, 2
 }
 f32sub $a0, $azero, $a0
 st32 $a0, $m11, $m15, 7 # 4-byte Folded Spill
 ld64 $ap3, $m1, $m15, 7
 {
  ld64 $ap3, $m1, $m15, 8
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 9
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 10
  f32v2add $ap1, $ap1, $ap3
 }
 {
  ld64 $ap3, $m1, $m15, 11
  f32v2add $ap1, $ap1, $ap3
 }
 st32 $m3, $m11, $m15, 0
 ld32 $a0, $m11, $m15, 0
 #APP
 put 9, $a5
 put 10, $a0
 #NO_APP
 f32v2add $ap1, $ap1, $ap3
 {
  ld32 $m4, $m13, $m15, 4
  f32add $a0, $a2, $a3
 }
 {
  cmpeq $m7, $m4, 1
  f32div $a0, $a0, $a1
 }
 f32add $a0, $a0, $a4
 #APP
 f32oorx $a0, $a0
 #NO_APP
 ld32 $m3, $m13, $m15, 1
 ld32 $m9, $m13, $m15, 2
 ld32 $a1, $m11, $m15, 7 # 4-byte Folded Reload
 st32 $a1, $m11, $m15, 8
 ld32 $m10, $m13, $m15, 3
 st32 $a0, $m11, $m15, 9
 ld32 $m8, $m13, $m15, 8
 ld32 $m1, $m13, $m15, 10
 st32 $m10, $m11, $m15, 6 # 4-byte Folded Spill
 brnz $m7, .Lcode5_BB0_4
 # %bb.3: # %for.body20.preheader.i
 brz $m1, .Lcode5_BB0_4
 # %bb.19: # %if.else.i.i
 shl $m7, $m0, 2
 cmpult $m6, $m7, $m2
 brz $m6, .Lcode5_BB0_24
 # %bb.20: # %for.body.i.i.preheader
 st32 $m1, $m11, $m15, 2 # 4-byte Folded Spill
 st32 $m0, $m11, $m15, 1 # 4-byte Folded Spill
 shl $m6, $m0, 3
 add $m0, $m11, 32
 st32 $m0, $m11, $m15, 5 # 4-byte Folded Spill
 add $m9, $m9, $m6
 add $m3, $m3, $m6
 add $m5, $m5, $m6
 setzi $m0, 1
 st32 $m0, $m11, $m15, 4 # 4-byte Folded Spill
 st32 $m8, $m11, $m15, 7 # 4-byte Folded Spill
 st32 $m4, $m11, $m15, 3 # 4-byte Folded Spill
.Lcode5_BB0_21: # %for.body.i.i
                                        # =>This Inner Loop Header: Depth=1
 shr $m0, $m7, 5
 mul $m0, $m0, $m4
 ld32 $m1, $m11, $m15, 7 # 4-byte Folded Reload
 add $m0, $m0, $m1
 shl $m0, $m0, 5
 mov $m4, $m2
 and $m2, $m7, 28
 or $m0, $m0, $m2
 add $m7, $m7, 24
 add $m0, $m10, $m0
 mov $m2, $m5
 add $m5, $m5, 48
 mov $m1, $m9
 add $m9, $m9, 48
 mov $m10, $m3
 ld32 $m6, $m11, $m15, 5 # 4-byte Folded Reload
 ld32 $m8, $m11, $m15, 4 # 4-byte Folded Reload
 #APP
 ld32 $a6, $m6, $m15, 0
 ld32 $a7, $m6, $m15, 1
 {
  rpt $m8, 20
  fnop
 }

 {
  ld32step $a0, $m15, $m2+=, 1
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  ld32step $a2, $m15, $m10+=, 1
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f16v2tof32 $ap1, $a2
 }

 {
  ld32step $a4, $m15, $m1+=, 1
  f32v2mul $ap0, $ap0, $ap1
 }

 {
  nop
  f16v2tof32 $ap1, $a4
 }

 {
  nop
  f32v2add $ap0, $ap0, $ap1
 }

 {
  nop
  f32v2tof16 $a5, $ap0
 }

 {
  ld32step $a0, $m15, $m2+=, 11
  f16v2tof8 $a5, $a5
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  ld32step $a2, $m15, $m10+=, 11
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f16v2tof32 $ap1, $a2
 }

 {
  ld32step $a4, $m15, $m1+=, 11
  f32v2mul $ap0, $ap0, $ap1
 }

 {
  nop
  f16v2tof32 $ap1, $a4
 }

 {
  nop
  f32v2add $ap0, $ap0, $ap1
 }

 {
  nop
  f32v2tof16 $a0, $ap0
 }

 {
  nop
  f16v2tof8 $a0, $a0
 }

 {
  nop
  sort4x16lo $a0, $a5, $a0
 }

 {
  st32step $a0, $m15, $m0+=, 6
  fnop
 }


 #NO_APP
 ld32 $m10, $m11, $m15, 6 # 4-byte Folded Reload
 mov $m2, $m4
 ld32 $m4, $m11, $m15, 3 # 4-byte Folded Reload
 add $m3, $m3, 48
 cmpult $m0, $m7, $m2
 brnz $m0, .Lcode5_BB0_21
 bri .Lcode5_BB0_22
.Lcode5_BB0_9: # %if.end.i.i
 shr $m3, $m2, 1
 cmpult $m2, $m0, $m3
 brz $m2, .Lcode5_BB0_10
 # %bb.11: # %if.end6.i.i
 {
  mov $m2, $m15
  zero $ap2
 }
 sub $m3, $m3, $m0
 add $m3, $m3, 5
 setzi $m4, 43691
 sort4x16lo $m6, $m3, $m15
 shr $m3, $m3, 16
 mul $m7, $m6, $m4
 mul $m4, $m3, $m4
 shr $m7, $m7, 16
 add $m4, $m4, $m7
 setzi $m7, 43690
 mul $m6, $m6, $m7
 mul $m3, $m3, $m7
 sort4x16lo $m7, $m4, $m15
 shr $m4, $m4, 16
 add $m6, $m6, $m7
 add $m3, $m3, $m4
 shr $m4, $m6, 16
 shl $m6, $m0, 2
 add $m3, $m3, $m4
 add $m4, $m5, $m6
 shr $m3, $m3, 2
 #APP
 {
  rpt $m3, 2
  fnop
 }

 {
  ld32step $a0, $m15, $m4+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap2, $ap2, $ap0
 }


 #NO_APP
 st64 $ap2, $m1, $m15, $m0
 exitz $m15
.Lcode5_BB0_16: # %if.end.i78.i
 {
  shr $m3, $m2, 1
  zero $ap3
 }
 cmpult $m2, $m0, $m3
 brz $m2, .Lcode5_BB0_18
 # %bb.17: # %if.end6.i84.i
 mov $m2, $m15
 {
  sub $m3, $m3, $m0
  f32sub $a3, $azero, $a0
 }
 add $m3, $m3, 5
 setzi $m4, 43691
 sort4x16lo $m6, $m3, $m15
 shr $m3, $m3, 16
 mul $m7, $m6, $m4
 mul $m4, $m3, $m4
 shr $m7, $m7, 16
 add $m4, $m4, $m7
 setzi $m7, 43690
 mul $m6, $m6, $m7
 mul $m3, $m3, $m7
 sort4x16lo $m7, $m4, $m15
 shr $m4, $m4, 16
 add $m6, $m6, $m7
 add $m3, $m3, $m4
 shr $m4, $m6, 16
 shl $m6, $m0, 2
 add $m3, $m3, $m4
 add $m4, $m5, $m6
 shr $m3, $m3, 2
 #APP
 mov $a4, $a3
 {
  rpt $m3, 4
  fnop
 }

 {
  ld32step $a0, $m15, $m4+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a4:B, $ap0
 }

 {
  nop
  f32v2mul $ap0, $ap0, $ap0
 }

 {
  nop
  f32v2add $ap3, $ap3, $ap0
 }


 #NO_APP
.Lcode5_BB0_18: # %_ZL7normSumPKDhS0_jjfb.exit87.i
 shl $m0, $m0, 3
 st64 $ap3, $m0, $m1, 6
 exitz $m15
.Lcode5_BB0_4: # %if.then.i90.i
 st32 $m1, $m11, $m15, 2 # 4-byte Folded Spill
 shr $m7, $m2, 2
 st32 $m0, $m11, $m15, 1 # 4-byte Folded Spill
 st32 $m8, $m11, $m15, 7 # 4-byte Folded Spill
 cmpult $m8, $m0, $m7
 brz $m8, .Lcode5_BB0_22
 # %bb.5: # %if.then2.i.i
 ld32 $m0, $m11, $m15, 1 # 4-byte Folded Reload
 sub $m8, $m7, $m0
 add $m1, $m11, 32
 st32 $m1, $m11, $m15, 5 # 4-byte Folded Spill
 add $m8, $m8, 5
 st32 $m9, $m11, $m15, 4 # 4-byte Folded Spill
 setzi $m9, 43691
 sort4x16lo $m10, $m8, $m15
 shr $m8, $m8, 16
 mul $m7, $m10, $m9
 mul $m9, $m8, $m9
 shr $m7, $m7, 16
 add $m7, $m9, $m7
 setzi $m9, 43690
 mul $m10, $m10, $m9
 mul $m8, $m8, $m9
 sort4x16lo $m9, $m7, $m15
 shr $m7, $m7, 16
 add $m9, $m10, $m9
 ld32 $m1, $m11, $m15, 7 # 4-byte Folded Reload
 mul $m10, $m1, $m2
 add $m7, $m8, $m7
 shr $m8, $m9, 16
 shl $m9, $m0, 2
 ld32 $m1, $m11, $m15, 6 # 4-byte Folded Reload
 add $m10, $m1, $m10
 add $m7, $m7, $m8
 shl $m6, $m0, 3
 add $m5, $m5, $m6
 add $m8, $m3, $m6
 ld32 $m0, $m11, $m15, 4 # 4-byte Folded Reload
 add $m6, $m0, $m6
 add $m9, $m10, $m9
 ld32 $m10, $m11, $m15, 6 # 4-byte Folded Reload
 shr $m7, $m7, 2
 ld32 $m0, $m11, $m15, 5 # 4-byte Folded Reload
 #APP
 ld32 $a6, $m0, $m15, 0
 ld32 $a7, $m0, $m15, 1
 {
  rpt $m7, 20
  fnop
 }

 {
  ld32step $a0, $m15, $m5+=, 1
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  ld32step $a2, $m15, $m8+=, 1
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f16v2tof32 $ap1, $a2
 }

 {
  ld32step $a4, $m15, $m6+=, 1
  f32v2mul $ap0, $ap0, $ap1
 }

 {
  nop
  f16v2tof32 $ap1, $a4
 }

 {
  nop
  f32v2add $ap0, $ap0, $ap1
 }

 {
  nop
  f32v2tof16 $a5, $ap0
 }

 {
  ld32step $a0, $m15, $m5+=, 11
  f16v2tof8 $a5, $a5
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  ld32step $a2, $m15, $m8+=, 11
  f32v2mul $ap0, $a7:B, $ap0
 }

 {
  nop
  f16v2tof32 $ap1, $a2
 }

 {
  ld32step $a4, $m15, $m6+=, 11
  f32v2mul $ap0, $ap0, $ap1
 }

 {
  nop
  f16v2tof32 $ap1, $a4
 }

 {
  nop
  f32v2add $ap0, $ap0, $ap1
 }

 {
  nop
  f32v2tof16 $a0, $ap0
 }

 {
  nop
  f16v2tof8 $a0, $a0
 }

 {
  nop
  sort4x16lo $a0, $a5, $a0
 }

 {
  st32step $a0, $m15, $m9+=, 6
  fnop
 }


 #NO_APP
.Lcode5_BB0_22: # %if.end26.i.i
 ld32 $m8, $m11, $m15, 7 # 4-byte Folded Reload
 ld32 $m0, $m11, $m15, 2 # 4-byte Folded Reload
 brz $m0, .Lcode5_BB0_27
 # %bb.23: # %if.end26.i.if.then28.i_crit_edge.i
 ld32 $m0, $m11, $m15, 1 # 4-byte Folded Reload
 shl $m7, $m0, 2
.Lcode5_BB0_24: # %if.then28.i.i
 add $m1, $m2, 31
 add $m0, $m7, $m2
 andc $m5, $m1, 31
 cmpult $m1, $m0, $m5
 brz $m1, .Lcode5_BB0_27
 # %bb.25: # %for.body38.i.i.preheader
 add $m1, $m7, $m2
 add $m1, $m1, 24
 mov $m3, $m2
 cmpult $m2, $m1, $m5
 movnz $m1, $m2, $m5
 sub $m1, $m1, $m7
 sub $m1, $m1, $m3
 add $m1, $m1, -24
 cmpeq $m2, $m1, 0
 setzi $m3, 1
 movnz $m3, $m2, $m1
 sub $m1, $m1, $m3
 setzi $m2, 43691
 sort4x16lo $m5, $m1, $m15
 shr $m1, $m1, 16
 mul $m6, $m5, $m2
 mul $m2, $m1, $m2
 shr $m6, $m6, 16
 add $m2, $m2, $m6
 setzi $m6, 43690
 sort4x16lo $m7, $m2, $m15
 mul $m5, $m5, $m6
 shr $m2, $m2, 16
 mul $m1, $m1, $m6
 add $m5, $m5, $m7
 add $m1, $m1, $m2
 shr $m2, $m5, 16
 add $m1, $m1, $m2
 shr $m1, $m1, 4
 add $m1, $m3, $m1
 add $m2, $m1, 1
 add $m2, $m2, -1
.Lcode5_BB0_26: # %for.body38.i.i
                                        # =>This Inner Loop Header: Depth=1
 shr $m1, $m0, 5
 mul $m1, $m1, $m4
 add $m1, $m1, $m8
 shl $m1, $m1, 5
 and $m3, $m0, 31
 or $m1, $m1, $m3
 st32 $azero, $m10, $m1, 0
 add $m0, $m0, 24
 brnzdec $m2, .Lcode5_BB0_26
.Lcode5_BB0_27: # %_ZN11LayerNormF87computeEj.exit
 exitz $m15
.Lcode5_BB0_10:
 zero $ap2
 st64 $ap2, $m1, $m15, $m0
 exitz $m15
.Lcode5_func_end0:
 .size __runCodelet_LayerNormF8, .Lcode5_func_end0-__runCodelet_LayerNormF8
 .section .stack_sizes,"o",@progbits,.text.__runCodelet_LayerNormF8
 .long .Lcode5_func_begin0
 .byte 40
 .section .text.__runCodelet_LayerNormF8,"ax",@progbits
                                        # -- End function
 .ident "clang version 16.0.0 (git@github.com:Software-GCAI/llvm-project.git 6343a843cd5af31429c62a83b6ba249a74d36969)"
 .section ".note.GNU-stack","",@progbits
 .addrsig
# 3901 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .section .text.layer_norm_f8,"ax",@progbits
 .globl layer_norm_f8
 .p2align 2
 .type layer_norm_f8,@function
layer_norm_f8:
 .supervisor
 add $m11, $m11, -160
 st32 $m3, $m11, $m15, 0



 st32 $m4, $m11, $m15, (1 + 0)
 st32 $m5, $m11, $m15, (2 + 0)
 st32 $m2, $m11, $m15, (3 + 0)
 st32 $m6, $m11, $m15, (4 + 0)
 st32 $m7, $m11, $m15, (5 + 0)
 add $m0, $m11, 64
 st32 $m0, $m11, $m15, (6 + 0)

 st32 $m15, $m11, $m15, 8
 st32 $m8, $m11, $m15, 9
 st32 $m9, $m11, $m15, 10

 setzi $m0, __runCodelet_LayerNormF8
.Lwrap5_row:
 setzi $m1, 0
.Lwrap5_stage:
 st32 $m1, $m11, $m15, (7 + 0)
 runall $m0, $m11, 0
 sync (2)
 add $m1, $m1, 1
 cmpeq $m2, $m1, 3
 brz $m2, .Lwrap5_stage
 shl $m2, $m7, 1
 ld32 $m3, $m11, $m15, 0
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 0

 ld32 $m3, $m11, $m15, 8
 add $m3, $m3, 1
 st32 $m3, $m11, $m15, 8
# 3954 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 sub $m6, $m6, 1
 brnz $m6, .Lwrap5_row
 add $m11, $m11, 160
 br $m10
 .size layer_norm_f8, .-layer_norm_f8
# 3976 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .file "3"
 .section .text.__runCodelet_AddLayerNormMoments,"ax",@progbits
 .globl __runCodelet_AddLayerNormMoments # -- Begin function __runCodelet_AddLayerNormMoments
 .p2align 2
 .type __runCodelet_AddLayerNormMoments,@function
__runCodelet_AddLayerNormMoments: # @__runCodelet_AddLayerNormMoments
 .worker
.Lcode6_func_begin0:
 # %bb.0: # %entry
 setzi $m6, 16
 cmpult $m6, $m6, __worker_stack_max_growth_plus_one
 brz $m6, _stackoverflow
 add $m11, $m12, -16
 get $m0, 1
 ld32 $m3, $m13, $m15, 4
 and $m1, $m0, 7
 ld32 $m0, $m13, $m15, 3
 ld32 $m2, $m13, $m15, 2
 brz $m3, .Lcode6_BB0_1
 # %bb.11: # %if.end.i
 ld64 $ap0, $m0, $m15, 0
 {
  ld64 $ap1, $m0, $m15, 1
  f32v2add $ap0, $ap0, $apzero
 }
 {
  ld64 $ap1, $m0, $m15, 2
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m0, $m15, 3
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m0, $m15, 4
  f32v2add $ap0, $ap0, $ap1
 }
 {
  ld64 $ap1, $m0, $m15, 5
  f32v2add $ap0, $ap0, $ap1
 }
 {
  cmpeq $m3, $m3, 1
  f32v2add $ap0, $ap0, $ap1
 }
 {
  st32 $m2, $m11, $m15, 1
  f32add $a0, $a0, $a1
 }
 ld32 $a1, $m11, $m15, 1
 f32fromui32 $a1, $a1
 {
  brz $m3, .Lcode6_BB0_18
  f32div $a0, $a0, $a1
 }
 # %bb.12: # %if.then15.i
 cmpult $m5, $m2, 96
 ld32 $m4, $m13, $m15, 6
 shl $m3, $m1, 3
 brnz $m5, .Lcode6_BB0_15
 # %bb.13: # %if.then15.i
 or $m5, $m2, $m4
 and $m5, $m5, 7
 brnz $m5, .Lcode6_BB0_15
 # %bb.14: # %if.then.i.i
 mov $m5, $m15
 {
  shr $m2, $m2, 2
  f32sub $a7, $azero, $a0
 }
 sub $m2, $m2, $m1
 add $m1, $m11, 8
 add $m2, $m2, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m2, $m15
 shr $m8, $m2, 16
 add $m2, $m4, $m3
 mul $m4, $m7, $m6
 mul $m6, $m8, $m6
 shr $m4, $m4, 16
 add $m4, $m6, $m4
 setzi $m6, 43690
 mul $m7, $m7, $m6
 mul $m6, $m8, $m6
 sort4x16lo $m8, $m4, $m15
 shr $m4, $m4, 16
 add $m7, $m7, $m8
 add $m4, $m6, $m4
 shr $m6, $m7, 16
 add $m4, $m4, $m6
 shr $m4, $m4, 2
 #APP
 setzi $a0, 8
 put 1, $a0
 mov $a6, $a7
 {
  rpt $m4, 5
  fnop
 }

 {
  ld64step $ap2, $m15, $m2+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a4
 }

 {
  nop
  f16v2tof32 $ap1, $a5
 }

 {
  nop
  f32v2add $ap0, $a6:B, $ap0
 }

 {
  nop
  f32v2add $ap1, $a6:B, $ap1
 }

 {
  nop
  f32v4sqacc $aq0
 }

 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m1, $m15, 0

 #NO_APP
 ld64 $ap3, $m11, $m15, 1
 st64 $ap3, $m3, $m0, 6
 exitz $m15
.Lcode6_BB0_1: # %if.then.i
 {
  add $m3, $m2, 7
  zero $ap0
 }
 shr $m3, $m3, 3
 cmpult $m6, $m1, $m3
 ld32 $m4, $m13, $m15, 0
 st64 $apzero, $m11, $m15, 1
 ld32 $m5, $m13, $m15, 5
 ld32 $m3, $m13, $m15, 6
 brz $m6, .Lcode6_BB0_10
 # %bb.2: # %if.end.i.i
 shr $m6, $m2, 3
 cmpult $m7, $m1, $m6
 brz $m7, .Lcode6_BB0_3
 # %bb.4: # %cond.true.i.i
 sub $m6, $m6, $m1
 add $m6, $m6, 5
 setzi $m7, 43691
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 mul $m9, $m8, $m7
 mul $m7, $m6, $m7
 shr $m9, $m9, 16
 add $m7, $m7, $m9
 setzi $m9, 43690
 sort4x16lo $m10, $m7, $m15
 mul $m8, $m8, $m9
 shr $m7, $m7, 16
 mul $m6, $m6, $m9
 add $m8, $m8, $m10
 add $m6, $m6, $m7
 shr $m7, $m8, 16
 add $m6, $m6, $m7
 shr $m6, $m6, 2
 bri .Lcode6_BB0_5
.Lcode6_BB0_18: # %if.else.i
 brz $m1, .Lcode6_BB0_19
 # %bb.20: # %_ZN19AddLayerNormMoments7computeEj.exit
 exitz $m15
.Lcode6_BB0_15: # %if.end.i60.i
 {
  shr $m5, $m2, 1
  zero $ap3
 }
 cmpult $m2, $m1, $m5
 brz $m2, .Lcode6_BB0_17
 # %bb.16: # %if.then10.i66.i
 mov $m2, $m15
 {
  sub $m5, $m5, $m1
  f32sub $a3, $azero, $a0
 }
 add $m5, $m5, 5
 setzi $m6, 43691
 sort4x16lo $m7, $m5, $m15
 shr $m5, $m5, 16
 mul $m8, $m7, $m6
 mul $m6, $m5, $m6
 shr $m8, $m8, 16
 add $m6, $m6, $m8
 setzi $m8, 43690
 mul $m7, $m7, $m8
 mul $m5, $m5, $m8
 sort4x16lo $m8, $m6, $m15
 shr $m6, $m6, 16
 add $m7, $m7, $m8
 add $m5, $m5, $m6
 shr $m6, $m7, 16
 add $m5, $m5, $m6
 shl $m1, $m1, 2
 shr $m5, $m5, 2
 add $m1, $m4, $m1
 #APP
 mov $a4, $a3
 {
  rpt $m5, 4
  fnop
 }

 {
  ld32step $a0, $m15, $m1+=, 6
  fnop
 }

 {
  nop
  f16v2tof32 $ap0, $a0
 }

 {
  nop
  f32v2add $ap0, $a4:B, $ap0
 }

 {
  nop
  f32v2mul $ap0, $ap0, $ap0
 }

 {
  nop
  f32v2add $ap3, $ap3, $ap0
 }


 #NO_APP
.Lcode6_BB0_17: # %_ZL7normSumPKDhS0_jjfb.exit.i
 st64 $ap3, $m3, $m0, 6
 exitz $m15
.Lcode6_BB0_19: # %for.body25.preheader.i
 ld64 $ap1, $m0, $m15, 6
 {
  ld64 $ap2, $m0, $m15, 7
  f32v2add $ap1, $ap1, $apzero
 }
 {
  ld64 $ap2, $m0, $m15, 8
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld64 $ap2, $m0, $m15, 9
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld64 $ap2, $m0, $m15, 10
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld64 $ap2, $m0, $m15, 11
  f32v2add $ap1, $ap1, $ap2
 }
 {
  ld32 $m0, $m13, $m15, 1
  f32v2add $ap1, $ap1, $ap2
 }
 f32add $a1, $a2, $a3
 st64 $ap0, $m0, $m15, 0
 exitz $m15
.Lcode6_BB0_3:
 mov $m6, $m15
.Lcode6_BB0_5: # %cond.end.i.i
 shl $m8, $m1, 4
 #APP
 setzi $a0, 8
 put 1, $a0
 #NO_APP
 shl $m7, $m1, 3
 add $m4, $m4, $m8
 add $m5, $m5, $m8
 add $m3, $m3, $m8
 brz $m6, .Lcode6_BB0_7
 # %bb.6: # %if.then10.i.i
 #APP
 {
  rpt $m6, 6
  fnop
 }

 {
  ld64step $ap0, $m15, $m4+=, 1
  fnop
 }

 {
  ld64step $ap1, $m15, $m4+=, 11
  fnop
 }

 {
  ld64step $ap2, $m15, $m5+=, 1
  fnop
 }

 {
  ld64step $ap3, $m15, $m5+=, 11
  f16v4add $ap0, $ap0, $ap2
 }

 {
  nop
  f16v4add $ap1, $ap1, $ap3
 }

 {
  st64step $ap0, $m15, $m3+=, 1
  fnop
 }

 {
  st64step $ap1, $m15, $m3+=, 11
  f16v8acc $aq0
 }


 #NO_APP
.Lcode6_BB0_7: # %if.end13.i.i
 mul $m6, $m6, 48
 add $m6, $m6, $m7
 cmpult $m2, $m6, $m2
 brz $m2, .Lcode6_BB0_9
 # %bb.8: # %if.then18.i.i
 #APP
 ld64 $ap0, $m4, $m15, 0
 ld64 $ap2, $m5, $m15, 0
 f16v4add $ap0, $ap0, $ap2
 zero $ap1
 {
  st64 $ap0, $m3, $m15, 0
  f16v8acc $aq0
 }


 #NO_APP
.Lcode6_BB0_9: # %if.end19.i.i
 add $m2, $m11, 8
 #APP
 f32v2gina $ap0, $apzero, 0
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 f32v2gina $ap1, $apzero, 0
 f32v2add $ap0, $ap0, $ap1
 st64 $ap0, $m2, $m15, 0

 #NO_APP
 ld64 $ap0, $m11, $m15, 1
.Lcode6_BB0_10: # %_ZL15normAddAndStorePKDhS0_PDhjj.exit.i
 st64 $ap0, $m0, $m15, $m1
 exitz $m15
.Lcode6_func_end0:
 .size __runCodelet_AddLayerNormMoments, .Lcode6_func_end0-__runCodelet_AddLayerNormMoments
 .section .stack_sizes,"o",@progbits,.text.__runCodelet_AddLayerNormMoments
 .long .Lcode6_func_begin0
 .byte 16
 .section .text.__runCodelet_AddLayerNormMoments,"ax",@progbits
                                        # -- End function
 .ident "clang version 16.0.0 (git@github.com:Software-GCAI/llvm-project.git 6343a843cd5af31429c62a83b6ba249a74d36969)"
 .section ".note.GNU-stack","",@progbits
 .addrsig
# 4374 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
 .text
 .allow_optimizations
 .section .text.add_layer_norm_moments,"ax",@progbits
 .globl add_layer_norm_moments
 .p2align 2
 .type add_layer_norm_moments,@function
add_layer_norm_moments:
 .supervisor
 add $m11, $m11, -128
 st32 $m3, $m11, $m15, 0
 st32 $m2, $m11, $m15, 1
 st32 $m7, $m11, $m15, 2
 add $m0, $m11, 32
 st32 $m0, $m11, $m15, 3

 st32 $m4, $m11, $m15, 5
 st32 $m5, $m11, $m15, 6

 setzi $m0, __runCodelet_AddLayerNormMoments
.Lwrap6_row:
 setzi $m1, 0
.Lwrap6_stage:
 st32 $m1, $m11, $m15, 4
 runall $m0, $m11, 0
 sync (2)
 add $m1, $m1, 1
 cmpeq $m2, $m1, 3
 brz $m2, .Lwrap6_stage
 ld32 $m3, $m11, $m15, 0
 shl $m2, $m7, 1
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 0

 ld32 $m3, $m11, $m15, 5
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 5
 ld32 $m3, $m11, $m15, 6
 add $m3, $m3, $m2
 st32 $m3, $m11, $m15, 6

 ld32 $m2, $m11, $m15, 1
 add $m2, $m2, 8
 st32 $m2, $m11, $m15, 1
 sub $m6, $m6, 1
 brnz $m6, .Lwrap6_row
 add $m11, $m11, 128
 br $m10
 .size add_layer_norm_moments, .-add_layer_norm_moments
# 4439 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S"
# 1 "/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S" 1

# 1 "/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f16.S" 1


 .text
 .allow_optimizations

 .set SYNC_COMPUTE_SET, (2)
 .set GELU_ALPHA_F16X2, 0x3a623a62
 .set GELU_BETA_F16X2, 0x29b929b9
 .set ONE_F16X2, 0x3c003c00
 .set HALF_F16X2, 0x38003800



 .macro GELU_PAIR value

 ld32 $a2, $mvertex_base, $m15, 3
 f16v2min $a3, \value, $a2
 ld32 $a2, $mvertex_base, $m15, 4
 f16v2max $a3, $a3, $a2
 f16v2mul $a2, $a3, $a3
 f16v2mul $a2, $a2, $a3
 f16v2mul $a2, $a4, $a2
 f16v2add $a2, $a3, $a2
 f16v2mul $a2, $a5, $a2
 f16v2tanh $a2, $a2
 f16v2add $a2, $a6, $a2
 f16v2mul $a2, $a7, $a2
 f16v2mul $a2, \value, $a2
 .endm

 .macro LOAD_GELU_CONSTANTS
 ldconst $a4, GELU_BETA_F16X2
 ldconst $a5, GELU_ALPHA_F16X2
 ldconst $a6, ONE_F16X2
 ldconst $a7, HALF_F16X2


 .endm

 .macro GELU_TWO_PAIRS offset







 ld32 $a2, $mvertex_base, $m15, 3
 f16v4min $a0:1, $a0:1, $a2:BL
 ld32 $a2, $mvertex_base, $m15, 4
 f16v4max $a0:1, $a0:1, $a2:BL
 f16v4mul $a2:3, $a0:1, $a0:1
 f16v4mul $a2:3, $a2:3, $a0:1
 f16v4mul $a2:3, $a4:BL, $a2:3
 f16v4add $a2:3, $a0:1, $a2:3
 f16v4mul $a2:3, $a5:BL, $a2:3
 { ld32 $a0, $m3, $m15, \offset
   f16v2tanh $a2, $a2 }
 { ld32 $a1, $m3, $m15, (\offset + 1)
   f16v2tanh $a3, $a3 }






 f16v4add $a2:3, $a6:BL, $a2:3
 f16v4mul $a2:3, $a7:BL, $a2:3
 f16v4mul $a2:3, $a0:1, $a2:3
 .endm

 .macro GELU_EIGHT_PAIRS
 ld32 $a0, $m3, $m15, 0
 ld32 $a1, $m3, $m15, 1
 GELU_TWO_PAIRS 0
 st32 $a2, $m2, $m15, 0
 st32 $a3, $m2, $m15, 1
 ld32 $a0, $m3, $m15, 2
 ld32 $a1, $m3, $m15, 3
 GELU_TWO_PAIRS 2
 st32 $a2, $m2, $m15, 2
 st32 $a3, $m2, $m15, 3
 ld32 $a0, $m3, $m15, 4
 ld32 $a1, $m3, $m15, 5
 GELU_TWO_PAIRS 4
 st32 $a2, $m2, $m15, 4
 st32 $a3, $m2, $m15, 5
 ld32 $a0, $m3, $m15, 6
 ld32 $a1, $m3, $m15, 7
 GELU_TWO_PAIRS 6
 st32 $a2, $m2, $m15, 6
 st32 $a3, $m2, $m15, 7
 .endm
# 3 "/srv/home/gc-sdk/ipu-stack/artifacts/gelu-broadcast-20260911/source/gelu_f8.S" 2


.text
.allow_optimizations
.section .text.gelu_f8,"ax",@progbits
.globl gelu_f8
.p2align 2
.type gelu_f8,@function
gelu_f8:
.supervisor
add $m11, $m11, -40
st32 $m2, $m11, $m15, 0
st32 $m3, $m11, $m15, 1
st32 $m4, $m11, $m15, 2
ldconst $m0, 0x48004800
st32 $m0, $m11, $m15, 3
ldconst $m0, 0xc800c800
st32 $m0, $m11, $m15, 4
sub $m6, 0, $m6
and $m6, $m6, 255
st32 $m6, $m11, $m15, 5
st32 $m5, $m11, $m15, 6
st32 $m7, $m11, $m15, 7
st32 $m8, $m11, $m15, 8
st32 $m9, $m11, $m15, 9
setzi $m0, .Lfp8_gelu_worker
runall $m0, $m11, 0
sync SYNC_COMPUTE_SET
add $m11, $m11, 40
br $m10
.size gelu_f8, .-gelu_f8

.macro GELU_FP8_QUAD offset, output_offset
ld32 $a0, $m3, $m15, \offset
ld32 $a1, $m3, $m15, (\offset + 1)
GELU_TWO_PAIRS \offset
f16v2tof8 $a2, $a2
f16v2tof8 $a3, $a3
sort4x16lo $a2, $a2, $a3
st32 $a2, $m2, $m15, \output_offset
.endm

.worker
.p2align 3
.Lfp8_gelu_worker:
setzi $a0, 2
put 9, $a0
ld32 $a0, $mvertex_base, $m15, 5
put 10, $a0
LOAD_GELU_CONSTANTS
setzi $m1, 0
ld32 $m7, $mvertex_base, $m15, 2
.Lfp8_gelu_row:
ld32 $m8, $mvertex_base, $m15, 6
ld32 $m3, $mvertex_base, $m15, 1
ld32 $m0, $mvertex_base, $m15, 8
mul $m0, $m1, $m0
shl $m0, $m0, 1
add $m3, $m3, $m0
get $m4, $WSR
and $m4, $m4, (0x00000007U)
shl $m4, $m4, 5
shl $m0, $m4, 1
add $m3, $m3, $m0
ld32 $m2, $mvertex_base, $m15, 0
ld32 $m0, $mvertex_base, $m15, 7
brz $m0, .Lfp8_gelu_linear
mul $m0, $m4, $m7
add $m2, $m2, $m0
shl $m0, $m1, 5
add $m2, $m2, $m0
setzi $m0, 192
mul $m9, $m7, $m0
bri .Lfp8_gelu_loop
.Lfp8_gelu_linear:
ld32 $m0, $mvertex_base, $m15, 9
mul $m0, $m1, $m0
add $m2, $m2, $m0
add $m2, $m2, $m4
setzi $m9, 192
.Lfp8_gelu_loop:
add $m0, $m4, 32
cmpult $m6, $m8, $m0
brnz $m6, .Lfp8_gelu_tail
GELU_FP8_QUAD 0, 0
GELU_FP8_QUAD 2, 1
GELU_FP8_QUAD 4, 2
GELU_FP8_QUAD 6, 3
GELU_FP8_QUAD 8, 4
GELU_FP8_QUAD 10, 5
GELU_FP8_QUAD 12, 6
GELU_FP8_QUAD 14, 7
add $m3, $m3, 384
add $m2, $m2, $m9
add $m4, $m4, 192
bri .Lfp8_gelu_loop
.Lfp8_gelu_tail:
cmpult $m6, $m4, $m8
brz $m6, .Lfp8_gelu_padding
GELU_FP8_QUAD 0, 0
add $m3, $m3, 8
add $m2, $m2, 4
add $m4, $m4, 4
bri .Lfp8_gelu_tail
.Lfp8_gelu_padding:
ld32 $m8, $mvertex_base, $m15, 9
.Lfp8_gelu_zero:
cmpult $m6, $m4, $m8
brz $m6, .Lfp8_gelu_next_row
st32 $m15, $m2, $m15, 0
add $m2, $m2, 4
add $m4, $m4, 4
and $m0, $m4, 31
brnz $m0, .Lfp8_gelu_zero

add $m4, $m4, 160
add $m2, $m2, $m9
add $m2, $m2, -32
bri .Lfp8_gelu_zero
.Lfp8_gelu_next_row:
add $m1, $m1, 1
cmpult $m6, $m1, $m7
brnz $m6, .Lfp8_gelu_row
exitz $m15
# 4440 "artifacts/gelu-broadcast-20260911/actual-check/elementwise_check.S" 2

>
Error: ELF processing failed: tool failed: popc exited with exit status: 1

Caused by:
    tool failed: popc exited with exit status: 1