#include "/srv/home/gc-sdk/ipu-stack/device/static_runtime.S"
#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 1
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 128
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_old_128
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lold_128_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lold_128_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lold_128_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lold_128_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_128_max_tail
	sub $m7, $m7, 1
#endif
.Lold_128_max_panel:
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	add $m3, $m3, $m8
	brnzdec $m7, .Lold_128_max_panel
#if !ATTENTION_FULL_BLOCK
.Lold_128_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_128_max_scalar
	sub $m7, $m7, 1
.Lold_128_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lold_128_max_pair
.Lold_128_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lold_128_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lold_128_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_128_exp_tail
	sub $m7, $m7, 1
#endif
	.macro EXP_old_128
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
	.macro QUAD_old_128
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
.Lold_128_exp_panel:
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_old_128
	.endr
	f16v4gacc $a2:3
	QUAD_old_128
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_128_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lold_128_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_128_exp_odd
	sub $m7, $m7, 1
.Lold_128_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_old_128
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lold_128_exp_pair
.Lold_128_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lold_128_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lold_128_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lold_128_zero_panels_setup
	sub $m7, $m7, 1
.Lold_128_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lold_128_zero_pair
.Lold_128_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lold_128_sum_ready
	sub $m7, $m7, 1
.Lold_128_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_128_zero_panel
.Lold_128_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lold_128_row
.Lold_128_done:
	exitz $m15

#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 1
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 128
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_new_128
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"
// Shared panel arithmetic for whole-row and segmented softmax workers.
	.macro MAXP_new_128
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	.endm
	.macro QUAD_new_128
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
	.macro EXPP_new_128
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_new_128
	.endr
	f16v4gacc $a2:3
	QUAD_new_128
	.endm
	.macro EXP_new_128
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys, m6 split-row flag.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	// m6 selects the cheaper row schedule, as priced by the host cost model.
	brz $m6, .Lnew_128_whole
	add $m11, $m11, -16
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
	st32 $m5, $m11, $m15, 3
	setzi $m0, .Lnew_128_split_max
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_128_split_exp
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_128_split_sum
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, 16
	br $m10
.Lnew_128_whole:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lnew_128_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lnew_128_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_128_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lnew_128_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_128_max_tail
	sub $m7, $m7, 1
#endif
.Lnew_128_max_panel:
	MAXP_new_128
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_128_max_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_128_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_128_max_scalar
	sub $m7, $m7, 1
.Lnew_128_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_128_max_pair
.Lnew_128_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lnew_128_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lnew_128_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_128_exp_tail
	sub $m7, $m7, 1
#endif
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
.Lnew_128_exp_panel:
	EXPP_new_128
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_128_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_128_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_128_exp_odd
	sub $m7, $m7, 1
.Lnew_128_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_128
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_128_exp_pair
.Lnew_128_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_128_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_128_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_128_zero_panels_setup
	sub $m7, $m7, 1
.Lnew_128_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_128_zero_pair
.Lnew_128_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lnew_128_sum_ready
	sub $m7, $m7, 1
.Lnew_128_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_128_zero_panel
.Lnew_128_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lnew_128_row
.Lnew_128_done:
	exitz $m15

// Three contiguous panel segments per row; scratch follows maxima/sums.

	.macro INIT_new_128
	ld32 $m5, $mvertex_base, $m15, 2
	get $m9, $WSR
	and $m9, $m9, CSR_W_WSR__CTXTID_M1__MASK
	setzi $m0, 3
	cmpult $m4, $m9, $m0
	brnz $m4, .Lnew_128_even_\@
	sub $m9, $m9, 3
	setzi $m4, 1
	bri .Lnew_128_parity_\@
.Lnew_128_even_\@:
	setzi $m4, 0
.Lnew_128_parity_\@:
	add $m8, $m5, -1
	shl $m8, $m8, 5
	.endm

	.macro ROW_new_128
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	// Three FP32 maxima and three sums use the existing extra 16 halves/row.
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 8
	mul $m6, $m5, $m0
	add $m6, $m6, $m2
	setzi $m0, 3
	mul $m0, $m4, $m0
	add $m0, $m0, $m9
	shl $m0, $m0, 2
	add $m6, $m6, $m0
	setzi $m0, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m0
	ld32 $m10, $mvertex_base, $m15, 3
	sub $m10, $m10, $m0
	cmpslt $m1, $m10, $mzero
	brz $m1, .Lnew_128_nonempty_\@
	setzi $m10, 0
.Lnew_128_nonempty_\@:
	// Capacity of this segment; m11 remains the worker stack pointer.
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	cmpult $m7, $m7, $m1
	brz $m7, .Lnew_128_capacity_\@
	setzi $m1, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
.Lnew_128_capacity_\@:
	cmpult $m7, $m1, $m10
	brz $m7, .Lnew_128_clamped_\@
	mov $m10, $m1
.Lnew_128_clamped_\@:
	mul $m0, $m0, $m5
	shl $m0, $m0, 1
	shl $m1, $m4, 5
	add $m0, $m0, $m1
	add $m2, $m2, $m0
	add $m3, $m3, $m0
	.endm

	.worker
	.p2align 3
.Lnew_128_split_max:
	INIT_new_128
.Lnew_128_split_max_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_128_done
	ROW_new_128
	ldconst $a6, 0xfbfffbff
	shr $m7, $m10, 4
	brz $m7, .Lnew_128_split_max_tail
	sub $m7, $m7, 1
.Lnew_128_split_max_panel:
	MAXP_new_128
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_128_split_max_panel
.Lnew_128_split_max_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_128_split_max_reduce
	and $m1, $m7, 1
	shr $m7, $m7, 1
	brz $m7, .Lnew_128_split_max_odd
	sub $m7, $m7, 1
.Lnew_128_split_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_128_split_max_pair
.Lnew_128_split_max_odd:
	brz $m1, .Lnew_128_split_max_reduce
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32tof16 $a0, $a0
	f16v2max $a6, $a6, $a0
.Lnew_128_split_max_reduce:
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_128_split_max_row

	.p2align 3
.Lnew_128_split_exp:
	INIT_new_128
.Lnew_128_split_exp_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_128_done
	ROW_new_128
	shl $m0, $m9, 2
	sub $m0, $m6, $m0
	ld32 $a0, $m0, $m15, 0
	ld32 $a1, $m0, $m15, 1
	ld32 $a2, $m0, $m15, 2
	f32max $a0, $a0, $a1
	f32max $a0, $a0, $a2
	f32tof16 $a4, $a0
	mov $a5, $a4
	brnz $m9, .Lnew_128_split_scale
	ldconst $a1, ATTENTION_SCALE_BITS
	f32mul $a2, $a0, $a1
	ld32 $m0, $mvertex_base, $m15, 0
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m1, $m5, $m1
	add $m0, $m0, $m1
	shl $m1, $m4, 2
	add $m0, $m0, $m1
	st32 $a2, $m0, $m15, 0
.Lnew_128_split_scale:
	ldconst $a0, ATTENTION_SCALE_BITS
	f32sub $a1, $azero, $a0
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	setzi $a6, 0
	setzi $a7, 0
	shr $m7, $m10, 4
	brz $m7, .Lnew_128_split_exp_tail
	sub $m7, $m7, 1
.Lnew_128_split_exp_panel:
	EXPP_new_128
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_128_split_exp_panel
.Lnew_128_split_exp_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_128_split_padding
	f16v2tof32 $a2:3, $a4
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a5, $a2, $a4
	f32sub $a5, $azero, $a5
	shr $m7, $m7, 1
	brz $m7, .Lnew_128_split_exp_odd
	sub $m7, $m7, 1
.Lnew_128_split_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_128
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_128_split_exp_pair
.Lnew_128_split_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_128_split_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_128_split_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_128_split_after_tail
	sub $m7, $m7, 1
.Lnew_128_split_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_128_split_zero_pair
.Lnew_128_split_after_tail:
	add $m2, $m2, $m8
.Lnew_128_split_padding:
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m7
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	cmpult $m0, $m7, $m1
	brz $m0, .Lnew_128_split_padding_capacity
	mov $m1, $m7
.Lnew_128_split_padding_capacity:
	shr $m7, $m1, 4
	add $m0, $m10, 15
	shr $m0, $m0, 4
	sub $m7, $m7, $m0
	brz $m7, .Lnew_128_split_store_sum
	sub $m7, $m7, 1
.Lnew_128_split_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_128_split_zero_panel
.Lnew_128_split_store_sum:
	setzi $m0, 12
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	f32add $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_128_split_exp_row

	.p2align 3
.Lnew_128_split_sum:
	ld32 $m5, $mvertex_base, $m15, 2
	ld32 $m2, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 4
	mul $m0, $m5, $m0
	add $m2, $m2, $m0
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
.Lnew_128_split_sum_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_128_done
	shl $m0, $m4, 2
	add $m3, $m2, $m0
	setzi $m0, 16
	mul $m0, $m5, $m0
	add $m6, $m2, $m0
	setzi $m0, 12
	mul $m0, $m4, $m0
	add $m6, $m6, $m0
	ld32 $a0, $m6, $m15, 0
	ld32 $a1, $m6, $m15, 1
	ld32 $a2, $m6, $m15, 2
	f32add $a0, $a0, $a1
	f32add $a0, $a0, $a2
	st32 $a0, $m3, $m15, 0
	add $m4, $m4, 6
	bri .Lnew_128_split_sum_row

#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 0
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 144
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_old_129
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lold_129_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lold_129_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lold_129_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lold_129_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_129_max_tail
	sub $m7, $m7, 1
#endif
.Lold_129_max_panel:
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	add $m3, $m3, $m8
	brnzdec $m7, .Lold_129_max_panel
#if !ATTENTION_FULL_BLOCK
.Lold_129_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_129_max_scalar
	sub $m7, $m7, 1
.Lold_129_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lold_129_max_pair
.Lold_129_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lold_129_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lold_129_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_129_exp_tail
	sub $m7, $m7, 1
#endif
	.macro EXP_old_129
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
	.macro QUAD_old_129
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
.Lold_129_exp_panel:
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_old_129
	.endr
	f16v4gacc $a2:3
	QUAD_old_129
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_129_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lold_129_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_129_exp_odd
	sub $m7, $m7, 1
.Lold_129_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_old_129
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lold_129_exp_pair
.Lold_129_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lold_129_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lold_129_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lold_129_zero_panels_setup
	sub $m7, $m7, 1
.Lold_129_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lold_129_zero_pair
.Lold_129_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lold_129_sum_ready
	sub $m7, $m7, 1
.Lold_129_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_129_zero_panel
.Lold_129_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lold_129_row
.Lold_129_done:
	exitz $m15

#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 0
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 144
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_new_129
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"
// Shared panel arithmetic for whole-row and segmented softmax workers.
	.macro MAXP_new_129
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	.endm
	.macro QUAD_new_129
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
	.macro EXPP_new_129
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_new_129
	.endr
	f16v4gacc $a2:3
	QUAD_new_129
	.endm
	.macro EXP_new_129
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys, m6 split-row flag.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	// m6 selects the cheaper row schedule, as priced by the host cost model.
	brz $m6, .Lnew_129_whole
	add $m11, $m11, -16
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
	st32 $m5, $m11, $m15, 3
	setzi $m0, .Lnew_129_split_max
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_129_split_exp
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_129_split_sum
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, 16
	br $m10
.Lnew_129_whole:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lnew_129_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lnew_129_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_129_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lnew_129_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_129_max_tail
	sub $m7, $m7, 1
#endif
.Lnew_129_max_panel:
	MAXP_new_129
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_129_max_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_129_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_129_max_scalar
	sub $m7, $m7, 1
.Lnew_129_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_129_max_pair
.Lnew_129_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lnew_129_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lnew_129_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_129_exp_tail
	sub $m7, $m7, 1
#endif
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
.Lnew_129_exp_panel:
	EXPP_new_129
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_129_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_129_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_129_exp_odd
	sub $m7, $m7, 1
.Lnew_129_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_129
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_129_exp_pair
.Lnew_129_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_129_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_129_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_129_zero_panels_setup
	sub $m7, $m7, 1
.Lnew_129_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_129_zero_pair
.Lnew_129_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lnew_129_sum_ready
	sub $m7, $m7, 1
.Lnew_129_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_129_zero_panel
.Lnew_129_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lnew_129_row
.Lnew_129_done:
	exitz $m15

// Three contiguous panel segments per row; scratch follows maxima/sums.

	.macro INIT_new_129
	ld32 $m5, $mvertex_base, $m15, 2
	get $m9, $WSR
	and $m9, $m9, CSR_W_WSR__CTXTID_M1__MASK
	setzi $m0, 3
	cmpult $m4, $m9, $m0
	brnz $m4, .Lnew_129_even_\@
	sub $m9, $m9, 3
	setzi $m4, 1
	bri .Lnew_129_parity_\@
.Lnew_129_even_\@:
	setzi $m4, 0
.Lnew_129_parity_\@:
	add $m8, $m5, -1
	shl $m8, $m8, 5
	.endm

	.macro ROW_new_129
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	// Three FP32 maxima and three sums use the existing extra 16 halves/row.
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 8
	mul $m6, $m5, $m0
	add $m6, $m6, $m2
	setzi $m0, 3
	mul $m0, $m4, $m0
	add $m0, $m0, $m9
	shl $m0, $m0, 2
	add $m6, $m6, $m0
	setzi $m0, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m0
	ld32 $m10, $mvertex_base, $m15, 3
	sub $m10, $m10, $m0
	cmpslt $m1, $m10, $mzero
	brz $m1, .Lnew_129_nonempty_\@
	setzi $m10, 0
.Lnew_129_nonempty_\@:
	// Capacity of this segment; m11 remains the worker stack pointer.
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	cmpult $m7, $m7, $m1
	brz $m7, .Lnew_129_capacity_\@
	setzi $m1, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
.Lnew_129_capacity_\@:
	cmpult $m7, $m1, $m10
	brz $m7, .Lnew_129_clamped_\@
	mov $m10, $m1
.Lnew_129_clamped_\@:
	mul $m0, $m0, $m5
	shl $m0, $m0, 1
	shl $m1, $m4, 5
	add $m0, $m0, $m1
	add $m2, $m2, $m0
	add $m3, $m3, $m0
	.endm

	.worker
	.p2align 3
.Lnew_129_split_max:
	INIT_new_129
.Lnew_129_split_max_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_129_done
	ROW_new_129
	ldconst $a6, 0xfbfffbff
	shr $m7, $m10, 4
	brz $m7, .Lnew_129_split_max_tail
	sub $m7, $m7, 1
.Lnew_129_split_max_panel:
	MAXP_new_129
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_129_split_max_panel
.Lnew_129_split_max_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_129_split_max_reduce
	and $m1, $m7, 1
	shr $m7, $m7, 1
	brz $m7, .Lnew_129_split_max_odd
	sub $m7, $m7, 1
.Lnew_129_split_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_129_split_max_pair
.Lnew_129_split_max_odd:
	brz $m1, .Lnew_129_split_max_reduce
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32tof16 $a0, $a0
	f16v2max $a6, $a6, $a0
.Lnew_129_split_max_reduce:
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_129_split_max_row

	.p2align 3
.Lnew_129_split_exp:
	INIT_new_129
.Lnew_129_split_exp_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_129_done
	ROW_new_129
	shl $m0, $m9, 2
	sub $m0, $m6, $m0
	ld32 $a0, $m0, $m15, 0
	ld32 $a1, $m0, $m15, 1
	ld32 $a2, $m0, $m15, 2
	f32max $a0, $a0, $a1
	f32max $a0, $a0, $a2
	f32tof16 $a4, $a0
	mov $a5, $a4
	brnz $m9, .Lnew_129_split_scale
	ldconst $a1, ATTENTION_SCALE_BITS
	f32mul $a2, $a0, $a1
	ld32 $m0, $mvertex_base, $m15, 0
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m1, $m5, $m1
	add $m0, $m0, $m1
	shl $m1, $m4, 2
	add $m0, $m0, $m1
	st32 $a2, $m0, $m15, 0
.Lnew_129_split_scale:
	ldconst $a0, ATTENTION_SCALE_BITS
	f32sub $a1, $azero, $a0
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	setzi $a6, 0
	setzi $a7, 0
	shr $m7, $m10, 4
	brz $m7, .Lnew_129_split_exp_tail
	sub $m7, $m7, 1
.Lnew_129_split_exp_panel:
	EXPP_new_129
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_129_split_exp_panel
.Lnew_129_split_exp_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_129_split_padding
	f16v2tof32 $a2:3, $a4
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a5, $a2, $a4
	f32sub $a5, $azero, $a5
	shr $m7, $m7, 1
	brz $m7, .Lnew_129_split_exp_odd
	sub $m7, $m7, 1
.Lnew_129_split_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_129
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_129_split_exp_pair
.Lnew_129_split_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_129_split_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_129_split_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_129_split_after_tail
	sub $m7, $m7, 1
.Lnew_129_split_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_129_split_zero_pair
.Lnew_129_split_after_tail:
	add $m2, $m2, $m8
.Lnew_129_split_padding:
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m7
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	cmpult $m0, $m7, $m1
	brz $m0, .Lnew_129_split_padding_capacity
	mov $m1, $m7
.Lnew_129_split_padding_capacity:
	shr $m7, $m1, 4
	add $m0, $m10, 15
	shr $m0, $m0, 4
	sub $m7, $m7, $m0
	brz $m7, .Lnew_129_split_store_sum
	sub $m7, $m7, 1
.Lnew_129_split_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_129_split_zero_panel
.Lnew_129_split_store_sum:
	setzi $m0, 12
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	f32add $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_129_split_exp_row

	.p2align 3
.Lnew_129_split_sum:
	ld32 $m5, $mvertex_base, $m15, 2
	ld32 $m2, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 4
	mul $m0, $m5, $m0
	add $m2, $m2, $m0
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
.Lnew_129_split_sum_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_129_done
	shl $m0, $m4, 2
	add $m3, $m2, $m0
	setzi $m0, 16
	mul $m0, $m5, $m0
	add $m6, $m2, $m0
	setzi $m0, 12
	mul $m0, $m4, $m0
	add $m6, $m6, $m0
	ld32 $a0, $m6, $m15, 0
	ld32 $a1, $m6, $m15, 1
	ld32 $a2, $m6, $m15, 2
	f32add $a0, $a0, $a1
	f32add $a0, $a0, $a2
	st32 $a0, $m3, $m15, 0
	add $m4, $m4, 6
	bri .Lnew_129_split_sum_row

#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 0
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 768
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_old_729
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lold_729_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lold_729_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lold_729_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lold_729_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_729_max_tail
	sub $m7, $m7, 1
#endif
.Lold_729_max_panel:
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	add $m3, $m3, $m8
	brnzdec $m7, .Lold_729_max_panel
#if !ATTENTION_FULL_BLOCK
.Lold_729_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_729_max_scalar
	sub $m7, $m7, 1
.Lold_729_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lold_729_max_pair
.Lold_729_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lold_729_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lold_729_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_729_exp_tail
	sub $m7, $m7, 1
#endif
	.macro EXP_old_729
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
	.macro QUAD_old_729
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
.Lold_729_exp_panel:
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_old_729
	.endr
	f16v4gacc $a2:3
	QUAD_old_729
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_729_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lold_729_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_729_exp_odd
	sub $m7, $m7, 1
.Lold_729_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_old_729
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lold_729_exp_pair
.Lold_729_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lold_729_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lold_729_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lold_729_zero_panels_setup
	sub $m7, $m7, 1
.Lold_729_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lold_729_zero_pair
.Lold_729_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lold_729_sum_ready
	sub $m7, $m7, 1
.Lold_729_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_729_zero_panel
.Lold_729_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lold_729_row
.Lold_729_done:
	exitz $m15

#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 0
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 768
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_new_729
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"
// Shared panel arithmetic for whole-row and segmented softmax workers.
	.macro MAXP_new_729
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	.endm
	.macro QUAD_new_729
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
	.macro EXPP_new_729
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_new_729
	.endr
	f16v4gacc $a2:3
	QUAD_new_729
	.endm
	.macro EXP_new_729
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys, m6 split-row flag.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	// m6 selects the cheaper row schedule, as priced by the host cost model.
	brz $m6, .Lnew_729_whole
	add $m11, $m11, -16
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
	st32 $m5, $m11, $m15, 3
	setzi $m0, .Lnew_729_split_max
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_729_split_exp
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_729_split_sum
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, 16
	br $m10
.Lnew_729_whole:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lnew_729_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lnew_729_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_729_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lnew_729_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_729_max_tail
	sub $m7, $m7, 1
#endif
.Lnew_729_max_panel:
	MAXP_new_729
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_729_max_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_729_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_729_max_scalar
	sub $m7, $m7, 1
.Lnew_729_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_729_max_pair
.Lnew_729_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lnew_729_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lnew_729_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_729_exp_tail
	sub $m7, $m7, 1
#endif
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
.Lnew_729_exp_panel:
	EXPP_new_729
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_729_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_729_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_729_exp_odd
	sub $m7, $m7, 1
.Lnew_729_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_729
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_729_exp_pair
.Lnew_729_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_729_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_729_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_729_zero_panels_setup
	sub $m7, $m7, 1
.Lnew_729_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_729_zero_pair
.Lnew_729_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lnew_729_sum_ready
	sub $m7, $m7, 1
.Lnew_729_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_729_zero_panel
.Lnew_729_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lnew_729_row
.Lnew_729_done:
	exitz $m15

// Three contiguous panel segments per row; scratch follows maxima/sums.

	.macro INIT_new_729
	ld32 $m5, $mvertex_base, $m15, 2
	get $m9, $WSR
	and $m9, $m9, CSR_W_WSR__CTXTID_M1__MASK
	setzi $m0, 3
	cmpult $m4, $m9, $m0
	brnz $m4, .Lnew_729_even_\@
	sub $m9, $m9, 3
	setzi $m4, 1
	bri .Lnew_729_parity_\@
.Lnew_729_even_\@:
	setzi $m4, 0
.Lnew_729_parity_\@:
	add $m8, $m5, -1
	shl $m8, $m8, 5
	.endm

	.macro ROW_new_729
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	// Three FP32 maxima and three sums use the existing extra 16 halves/row.
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 8
	mul $m6, $m5, $m0
	add $m6, $m6, $m2
	setzi $m0, 3
	mul $m0, $m4, $m0
	add $m0, $m0, $m9
	shl $m0, $m0, 2
	add $m6, $m6, $m0
	setzi $m0, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m0
	ld32 $m10, $mvertex_base, $m15, 3
	sub $m10, $m10, $m0
	cmpslt $m1, $m10, $mzero
	brz $m1, .Lnew_729_nonempty_\@
	setzi $m10, 0
.Lnew_729_nonempty_\@:
	// Capacity of this segment; m11 remains the worker stack pointer.
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	cmpult $m7, $m7, $m1
	brz $m7, .Lnew_729_capacity_\@
	setzi $m1, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
.Lnew_729_capacity_\@:
	cmpult $m7, $m1, $m10
	brz $m7, .Lnew_729_clamped_\@
	mov $m10, $m1
.Lnew_729_clamped_\@:
	mul $m0, $m0, $m5
	shl $m0, $m0, 1
	shl $m1, $m4, 5
	add $m0, $m0, $m1
	add $m2, $m2, $m0
	add $m3, $m3, $m0
	.endm

	.worker
	.p2align 3
.Lnew_729_split_max:
	INIT_new_729
.Lnew_729_split_max_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_729_done
	ROW_new_729
	ldconst $a6, 0xfbfffbff
	shr $m7, $m10, 4
	brz $m7, .Lnew_729_split_max_tail
	sub $m7, $m7, 1
.Lnew_729_split_max_panel:
	MAXP_new_729
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_729_split_max_panel
.Lnew_729_split_max_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_729_split_max_reduce
	and $m1, $m7, 1
	shr $m7, $m7, 1
	brz $m7, .Lnew_729_split_max_odd
	sub $m7, $m7, 1
.Lnew_729_split_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_729_split_max_pair
.Lnew_729_split_max_odd:
	brz $m1, .Lnew_729_split_max_reduce
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32tof16 $a0, $a0
	f16v2max $a6, $a6, $a0
.Lnew_729_split_max_reduce:
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_729_split_max_row

	.p2align 3
.Lnew_729_split_exp:
	INIT_new_729
.Lnew_729_split_exp_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_729_done
	ROW_new_729
	shl $m0, $m9, 2
	sub $m0, $m6, $m0
	ld32 $a0, $m0, $m15, 0
	ld32 $a1, $m0, $m15, 1
	ld32 $a2, $m0, $m15, 2
	f32max $a0, $a0, $a1
	f32max $a0, $a0, $a2
	f32tof16 $a4, $a0
	mov $a5, $a4
	brnz $m9, .Lnew_729_split_scale
	ldconst $a1, ATTENTION_SCALE_BITS
	f32mul $a2, $a0, $a1
	ld32 $m0, $mvertex_base, $m15, 0
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m1, $m5, $m1
	add $m0, $m0, $m1
	shl $m1, $m4, 2
	add $m0, $m0, $m1
	st32 $a2, $m0, $m15, 0
.Lnew_729_split_scale:
	ldconst $a0, ATTENTION_SCALE_BITS
	f32sub $a1, $azero, $a0
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	setzi $a6, 0
	setzi $a7, 0
	shr $m7, $m10, 4
	brz $m7, .Lnew_729_split_exp_tail
	sub $m7, $m7, 1
.Lnew_729_split_exp_panel:
	EXPP_new_729
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_729_split_exp_panel
.Lnew_729_split_exp_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_729_split_padding
	f16v2tof32 $a2:3, $a4
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a5, $a2, $a4
	f32sub $a5, $azero, $a5
	shr $m7, $m7, 1
	brz $m7, .Lnew_729_split_exp_odd
	sub $m7, $m7, 1
.Lnew_729_split_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_729
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_729_split_exp_pair
.Lnew_729_split_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_729_split_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_729_split_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_729_split_after_tail
	sub $m7, $m7, 1
.Lnew_729_split_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_729_split_zero_pair
.Lnew_729_split_after_tail:
	add $m2, $m2, $m8
.Lnew_729_split_padding:
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m7
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	cmpult $m0, $m7, $m1
	brz $m0, .Lnew_729_split_padding_capacity
	mov $m1, $m7
.Lnew_729_split_padding_capacity:
	shr $m7, $m1, 4
	add $m0, $m10, 15
	shr $m0, $m0, 4
	sub $m7, $m7, $m0
	brz $m7, .Lnew_729_split_store_sum
	sub $m7, $m7, 1
.Lnew_729_split_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_729_split_zero_panel
.Lnew_729_split_store_sum:
	setzi $m0, 12
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	f32add $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_729_split_exp_row

	.p2align 3
.Lnew_729_split_sum:
	ld32 $m5, $mvertex_base, $m15, 2
	ld32 $m2, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 4
	mul $m0, $m5, $m0
	add $m2, $m2, $m0
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
.Lnew_729_split_sum_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_729_done
	shl $m0, $m4, 2
	add $m3, $m2, $m0
	setzi $m0, 16
	mul $m0, $m5, $m0
	add $m6, $m2, $m0
	setzi $m0, 12
	mul $m0, $m4, $m0
	add $m6, $m6, $m0
	ld32 $a0, $m6, $m15, 0
	ld32 $a1, $m6, $m15, 1
	ld32 $a2, $m6, $m15, 2
	f32add $a0, $a0, $a1
	f32add $a0, $a0, $a2
	st32 $a0, $m3, $m15, 0
	add $m4, $m4, 6
	bri .Lnew_729_split_sum_row

#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 1
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 768
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_old_768
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lold_768_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lold_768_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lold_768_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lold_768_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_768_max_tail
	sub $m7, $m7, 1
#endif
.Lold_768_max_panel:
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	add $m3, $m3, $m8
	brnzdec $m7, .Lold_768_max_panel
#if !ATTENTION_FULL_BLOCK
.Lold_768_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_768_max_scalar
	sub $m7, $m7, 1
.Lold_768_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lold_768_max_pair
.Lold_768_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lold_768_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lold_768_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lold_768_exp_tail
	sub $m7, $m7, 1
#endif
	.macro EXP_old_768
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
	.macro QUAD_old_768
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
.Lold_768_exp_panel:
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_old_768
	.endr
	f16v4gacc $a2:3
	QUAD_old_768
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_768_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lold_768_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lold_768_exp_odd
	sub $m7, $m7, 1
.Lold_768_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_old_768
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lold_768_exp_pair
.Lold_768_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lold_768_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lold_768_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lold_768_zero_panels_setup
	sub $m7, $m7, 1
.Lold_768_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lold_768_zero_pair
.Lold_768_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lold_768_sum_ready
	sub $m7, $m7, 1
.Lold_768_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lold_768_zero_panel
.Lold_768_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lold_768_row
.Lold_768_done:
	exitz $m15

#undef ATTENTION_FULL_BLOCK
#define ATTENTION_FULL_BLOCK 1
#undef ATTENTION_KEY_BLOCK_COLUMNS
#define ATTENTION_KEY_BLOCK_COLUMNS 768
#undef ATTENTION_SCALE_BITS
#define ATTENTION_SCALE_BITS 0x3df15bf0
#undef ATTENTION_SOFTMAX_SYMBOL
#define ATTENTION_SOFTMAX_SYMBOL softmax_new_768
#undef SOFTMAX_FRAME_BYTES
#include "arch/gc_tile_defines.h"
// Shared panel arithmetic for whole-row and segmented softmax workers.
	.macro MAXP_new_768
	mov $a7, $a6
	ld64step $a0:1, $mzero, $m3+=, 1
	.rept 3
	{ ld64step $a0:1, $mzero, $m3+=, 1
	  f16v4max $a6:7, $a6:7, $a0:1 }
	.endr
	f16v4max $a6:7, $a6:7, $a0:1
	f16v2max $a6, $a6, $a7
	.endm
	.macro QUAD_new_768
	f16v2exp $a2, $a2
	f16v2exp $a3, $a3
	{ st32step $a2, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a2 }
	f32v2add $a6:7, $a6:7, $a0:1
	{ st32step $a3, $mzero, $m2+=, 1
	  f16v2tof32 $a0:1, $a3 }
	f32v2add $a6:7, $a6:7, $a0:1
	.endm
	.macro EXPP_new_768
	// Prime with zero accumulators so the discarded readout is finite.
	// MIX then returns each preceding quad while starting the next one.
	setzi $a0, 1 << CSR_W_FP_CLR__ZAACC__SHIFT
	uput $FP_CLR, $a0
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	.rept 3
	ld64step $a0:1, $mzero, $m3+=, 1
	f16v4mix $a2:3, $a0:1, $a4:5
	QUAD_new_768
	.endr
	f16v4gacc $a2:3
	QUAD_new_768
	.endm
	.macro EXP_new_768
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	.endm

// AMP-left panel order; FP16 probabilities with FP32 maxima and sums.
// m2 weights, m3 scores, m4 query rows, m5 valid keys, m6 split-row flag.
#if ATTENTION_FULL_BLOCK
#define SOFTMAX_FRAME_BYTES 12
#else
#define SOFTMAX_FRAME_BYTES 16
#endif
	.section .text.ATTENTION_SOFTMAX_SYMBOL,"ax",@progbits
	.globl ATTENTION_SOFTMAX_SYMBOL
	.p2align 2
	.type ATTENTION_SOFTMAX_SYMBOL,@function
ATTENTION_SOFTMAX_SYMBOL:
	.supervisor
	// m6 selects the cheaper row schedule, as priced by the host cost model.
	brz $m6, .Lnew_768_whole
	add $m11, $m11, -16
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
	st32 $m5, $m11, $m15, 3
	setzi $m0, .Lnew_768_split_max
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_768_split_exp
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	setzi $m0, .Lnew_768_split_sum
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, 16
	br $m10
.Lnew_768_whole:
	.supervisor
	add $m11, $m11, -SOFTMAX_FRAME_BYTES
	st32 $m2, $m11, $m15, 0
	st32 $m3, $m11, $m15, 1
	st32 $m4, $m11, $m15, 2
#if !ATTENTION_FULL_BLOCK
	st32 $m5, $m11, $m15, 3
#endif
	setzi $m0, .Lnew_768_worker
	runall $m0, $m11, 0
	sync TEXCH_SYNCZONE_LOCAL
	add $m11, $m11, SOFTMAX_FRAME_BYTES
	br $m10
	.size ATTENTION_SOFTMAX_SYMBOL, .-ATTENTION_SOFTMAX_SYMBOL

	.worker
	.p2align 3
.Lnew_768_worker:
	ld32 $m5, $mvertex_base, $m15, 2
#if !ATTENTION_FULL_BLOCK
	ld32 $m10, $mvertex_base, $m15, 3
#endif
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_768_done
	add $m8, $m5, -1
	shl $m8, $m8, 5
.Lnew_768_row:
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	shl $m0, $m4, 5
	add $m3, $m3, $m0
	add $m2, $m2, $m0
	mov $m9, $m3
	// The maximum of finite FP16 inputs is exactly representable in FP16.
	ldconst $a6, 0xfbfffbff
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_768_max_tail
	sub $m7, $m7, 1
#endif
.Lnew_768_max_panel:
	MAXP_new_768
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_768_max_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_768_max_tail:
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_768_max_scalar
	sub $m7, $m7, 1
.Lnew_768_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_768_max_pair
.Lnew_768_max_scalar:
#endif
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
#if !ATTENTION_FULL_BLOCK
	and $m0, $m10, 1
	brz $m0, .Lnew_768_max_ready
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32max $a6, $a6, $a0
.Lnew_768_max_ready:
#endif
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a7, $a6, $a4
	// Persistent maxima/denominators follow the packed weight matrix.
	ld32 $m6, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	shl $m0, $m4, 2
	add $m6, $m6, $m0
	st32 $a7, $m6, $m15, 0
	f32sub $a5, $azero, $a7
	f32tof16 $a2, $a6
	setzi $a6, 0
	setzi $a7, 0
	mov $m3, $m9
#if ATTENTION_FULL_BLOCK
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
#else
	shr $m7, $m10, 4
	brz $m7, .Lnew_768_exp_tail
	sub $m7, $m7, 1
#endif
	// TAS holds +/- the half scale. MIX forms the difference in FP32,
	// avoiding an overflowing intermediate FP16 subtraction.
	mov $a0, $a4
	f32sub $a1, $azero, $a4
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	mov $a4, $a2
	mov $a5, $a2
.Lnew_768_exp_panel:
	EXPP_new_768
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_768_exp_panel
#if !ATTENTION_FULL_BLOCK
.Lnew_768_exp_tail:
	ldconst $a4, ATTENTION_SCALE_BITS
	ld32 $a5, $m6, $m15, 0
	f32sub $a5, $azero, $a5
	and $m7, $m10, 15
	shr $m7, $m7, 1
	brz $m7, .Lnew_768_exp_odd
	sub $m7, $m7, 1
.Lnew_768_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_768
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_768_exp_pair
.Lnew_768_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_768_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	// Mask the unused lane before exponentiation; it contributes exactly zero.
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_768_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_768_zero_panels_setup
	sub $m7, $m7, 1
.Lnew_768_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_768_zero_pair
.Lnew_768_zero_panels_setup:
	add $m2, $m2, $m8
	shr $m0, $m10, 4
	setzi $m7, ATTENTION_KEY_BLOCK_COLUMNS / 16 - 1
	sub $m7, $m7, $m0
	brz $m7, .Lnew_768_sum_ready
	sub $m7, $m7, 1
.Lnew_768_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_768_zero_panel
.Lnew_768_sum_ready:
#endif
	f32add $a6, $a6, $a7
	shl $m0, $m5, 2
	add $m6, $m6, $m0
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 6
	cmpult $m0, $m4, $m5
	brnz $m0, .Lnew_768_row
.Lnew_768_done:
	exitz $m15

// Three contiguous panel segments per row; scratch follows maxima/sums.

	.macro INIT_new_768
	ld32 $m5, $mvertex_base, $m15, 2
	get $m9, $WSR
	and $m9, $m9, CSR_W_WSR__CTXTID_M1__MASK
	setzi $m0, 3
	cmpult $m4, $m9, $m0
	brnz $m4, .Lnew_768_even_\@
	sub $m9, $m9, 3
	setzi $m4, 1
	bri .Lnew_768_parity_\@
.Lnew_768_even_\@:
	setzi $m4, 0
.Lnew_768_parity_\@:
	add $m8, $m5, -1
	shl $m8, $m8, 5
	.endm

	.macro ROW_new_768
	ld32 $m2, $mvertex_base, $m15, 0
	ld32 $m3, $mvertex_base, $m15, 1
	// Three FP32 maxima and three sums use the existing extra 16 halves/row.
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 8
	mul $m6, $m5, $m0
	add $m6, $m6, $m2
	setzi $m0, 3
	mul $m0, $m4, $m0
	add $m0, $m0, $m9
	shl $m0, $m0, 2
	add $m6, $m6, $m0
	setzi $m0, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m0
	ld32 $m10, $mvertex_base, $m15, 3
	sub $m10, $m10, $m0
	cmpslt $m1, $m10, $mzero
	brz $m1, .Lnew_768_nonempty_\@
	setzi $m10, 0
.Lnew_768_nonempty_\@:
	// Capacity of this segment; m11 remains the worker stack pointer.
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	cmpult $m7, $m7, $m1
	brz $m7, .Lnew_768_capacity_\@
	setzi $m1, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
.Lnew_768_capacity_\@:
	cmpult $m7, $m1, $m10
	brz $m7, .Lnew_768_clamped_\@
	mov $m10, $m1
.Lnew_768_clamped_\@:
	mul $m0, $m0, $m5
	shl $m0, $m0, 1
	shl $m1, $m4, 5
	add $m0, $m0, $m1
	add $m2, $m2, $m0
	add $m3, $m3, $m0
	.endm

	.worker
	.p2align 3
.Lnew_768_split_max:
	INIT_new_768
.Lnew_768_split_max_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_768_done
	ROW_new_768
	ldconst $a6, 0xfbfffbff
	shr $m7, $m10, 4
	brz $m7, .Lnew_768_split_max_tail
	sub $m7, $m7, 1
.Lnew_768_split_max_panel:
	MAXP_new_768
	add $m3, $m3, $m8
	brnzdec $m7, .Lnew_768_split_max_panel
.Lnew_768_split_max_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_768_split_max_reduce
	and $m1, $m7, 1
	shr $m7, $m7, 1
	brz $m7, .Lnew_768_split_max_odd
	sub $m7, $m7, 1
.Lnew_768_split_max_pair:
	ld32step $a0, $mzero, $m3+=, 1
	f16v2max $a6, $a6, $a0
	brnzdec $m7, .Lnew_768_split_max_pair
.Lnew_768_split_max_odd:
	brz $m1, .Lnew_768_split_max_reduce
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32tof16 $a0, $a0
	f16v2max $a6, $a6, $a0
.Lnew_768_split_max_reduce:
	f16v2tof32 $a6:7, $a6
	f32max $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_768_split_max_row

	.p2align 3
.Lnew_768_split_exp:
	INIT_new_768
.Lnew_768_split_exp_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_768_done
	ROW_new_768
	shl $m0, $m9, 2
	sub $m0, $m6, $m0
	ld32 $a0, $m0, $m15, 0
	ld32 $a1, $m0, $m15, 1
	ld32 $a2, $m0, $m15, 2
	f32max $a0, $a0, $a1
	f32max $a0, $a0, $a2
	f32tof16 $a4, $a0
	mov $a5, $a4
	brnz $m9, .Lnew_768_split_scale
	ldconst $a1, ATTENTION_SCALE_BITS
	f32mul $a2, $a0, $a1
	ld32 $m0, $mvertex_base, $m15, 0
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS * 2
	mul $m1, $m5, $m1
	add $m0, $m0, $m1
	shl $m1, $m4, 2
	add $m0, $m0, $m1
	st32 $a2, $m0, $m15, 0
.Lnew_768_split_scale:
	ldconst $a0, ATTENTION_SCALE_BITS
	f32sub $a1, $azero, $a0
	f32v2tof16 $a0, $a0:1
	uput $TAS, $a0
	setzi $a6, 0
	setzi $a7, 0
	shr $m7, $m10, 4
	brz $m7, .Lnew_768_split_exp_tail
	sub $m7, $m7, 1
.Lnew_768_split_exp_panel:
	EXPP_new_768
	add $m3, $m3, $m8
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_768_split_exp_panel
.Lnew_768_split_exp_tail:
	and $m7, $m10, 15
	brz $m7, .Lnew_768_split_padding
	f16v2tof32 $a2:3, $a4
	ldconst $a4, ATTENTION_SCALE_BITS
	f32mul $a5, $a2, $a4
	f32sub $a5, $azero, $a5
	shr $m7, $m7, 1
	brz $m7, .Lnew_768_split_exp_odd
	sub $m7, $m7, 1
.Lnew_768_split_exp_pair:
	ld32step $a0, $mzero, $m3+=, 1
	EXP_new_768
	f32v2add $a6:7, $a6:7, $a2:3
	brnzdec $m7, .Lnew_768_split_exp_pair
.Lnew_768_split_exp_odd:
	and $m0, $m10, 1
	brz $m0, .Lnew_768_split_zero_tail
	ld32 $a0, $m3, $m15, 0
	f16v2tof32 $a0:1, $a0
	f32v2mul $a0:1, $a4:B, $a0:1
	f32v2add $a0:1, $a5:B, $a0:1
	ldconst $a1, 0xc77fe000
	f32v2tof16 $a0, $a0:1
	f16v2exp $a0, $a0
	{ st32step $a0, $mzero, $m2+=, 1
	  f16v2tof32 $a2:3, $a0 }
	f32v2add $a6:7, $a6:7, $a2:3
.Lnew_768_split_zero_tail:
	and $m7, $m10, 15
	add $m7, $m7, 1
	shr $m7, $m7, 1
	setzi $m0, 8
	sub $m7, $m0, $m7
	brz $m7, .Lnew_768_split_after_tail
	sub $m7, $m7, 1
.Lnew_768_split_zero_pair:
	st32step $mzero, $mzero, $m2+=, 1
	brnzdec $m7, .Lnew_768_split_zero_pair
.Lnew_768_split_after_tail:
	add $m2, $m2, $m8
.Lnew_768_split_padding:
	setzi $m7, ((ATTENTION_KEY_BLOCK_COLUMNS + 47) / 48) * 16
	mul $m0, $m9, $m7
	setzi $m1, ATTENTION_KEY_BLOCK_COLUMNS
	sub $m1, $m1, $m0
	cmpult $m0, $m7, $m1
	brz $m0, .Lnew_768_split_padding_capacity
	mov $m1, $m7
.Lnew_768_split_padding_capacity:
	shr $m7, $m1, 4
	add $m0, $m10, 15
	shr $m0, $m0, 4
	sub $m7, $m7, $m0
	brz $m7, .Lnew_768_split_store_sum
	sub $m7, $m7, 1
.Lnew_768_split_zero_panel:
	.rept 8
	st32step $mzero, $mzero, $m2+=, 1
	.endr
	add $m2, $m2, $m8
	brnzdec $m7, .Lnew_768_split_zero_panel
.Lnew_768_split_store_sum:
	setzi $m0, 12
	mul $m0, $m5, $m0
	add $m6, $m6, $m0
	f32add $a6, $a6, $a7
	st32 $a6, $m6, $m15, 0
	add $m4, $m4, 2
	bri .Lnew_768_split_exp_row

	.p2align 3
.Lnew_768_split_sum:
	ld32 $m5, $mvertex_base, $m15, 2
	ld32 $m2, $mvertex_base, $m15, 0
	setzi $m0, ATTENTION_KEY_BLOCK_COLUMNS * 2 + 4
	mul $m0, $m5, $m0
	add $m2, $m2, $m0
	get $m4, $WSR
	and $m4, $m4, CSR_W_WSR__CTXTID_M1__MASK
.Lnew_768_split_sum_row:
	cmpult $m0, $m4, $m5
	brz $m0, .Lnew_768_done
	shl $m0, $m4, 2
	add $m3, $m2, $m0
	setzi $m0, 16
	mul $m0, $m5, $m0
	add $m6, $m2, $m0
	setzi $m0, 12
	mul $m0, $m4, $m0
	add $m6, $m6, $m0
	ld32 $a0, $m6, $m15, 0
	ld32 $a1, $m6, $m15, 1
	ld32 $a2, $m6, $m15, 2
	f32add $a0, $a0, $a1
	f32add $a0, $a0, $a2
	st32 $a0, $m3, $m15, 0
	add $m4, $m4, 6
	bri .Lnew_768_split_sum_row