IPU Profile

1472 tiles, 110990 samples, 23 652 / 378 972 selected range, 355 320 cycles, 1.50 GHz
Flamegraph
Tilewise Timeline
compute tx rx tx/rx partner bus exchange idle sync multicast / paired \
Selected samples136128
Selected total522 960 522
Operations4
Longest range54 702 / 73 470
Longest ownertile 60 operation.2
Estimated useful work by kernel

Useful efficiency = useful issue-cycle equivalents / measured tile cycles. AMP uses peak FLOPs; other kernels use arithmetic instructions or dense-copy throughput. Lane occupancy excludes known padding. Coverage is the fraction of measured cycles with estimates; cut samples, legacy profiles, and unsupported kernels are unavailable. Values above 100% indicate model mismatch. Device useful includes idle tiles over the kernel’s interval union (a lower bound with partial coverage). Sorted by total tile cycles; click a kernel to focus the profile.

KernelTile cyclesUseful efficiencyWork cyclesLane occupancyCoverageDevice useful
68 935 68012.9%15.2%85.4%100.0%11.7%
68 544 00013.0%15.2%85.4%100.0%11.8%
64 703 23251.8%51.8%100.0%100.0%50.5%
58 361 856n/an/an/a0.0%n/a
37 856 16072.4%73.1%99.0%100.0%33.6%
25 108 27271.5%72.2%99.0%100.0%22.1%
5 883 8408.5%8.5%100.0%100.0%2.6%
5 644 80011.4%13.3%85.4%100.0%0.9%
5 612 54411.5%13.4%85.4%100.0%0.9%
5 183 28024.5%24.5%100.0%100.0%7.0%
4 177 53629.3%30.4%96.3%100.0%28.5%
3 857 7608.5%8.5%100.0%100.0%1.7%
3 361 92012.9%12.9%100.0%100.0%4.4%
1 835 922n/an/an/a0.0%n/a
1 320 00034.1%34.1%100.0%100.0%5.4%
758 496n/an/an/a0.0%n/a
276 86411.3%11.3%100.0%100.0%0.3%
216 9607.4%18.9%39.1%100.0%0.2%
147 4564.2%7.6%56.3%100.0%0.0%
96 6724.2%7.5%56.3%100.0%0.0%
6 132n/an/an/a0.0%n/a
1 086n/an/an/a0.0%n/a