* `and $mDst0, $mSrc0, $mSrc1`
* `and $mDst0, $mSrc0, zimm12`
* `and $aDst0, $aSrc0, $aSrc1`
* `and $aDst0, $aSrc0, zimm12`
* `and $aDst0, $aSrc0, immz12`

Bitwise logical AND of two source register values, or 1 source register
and 1 *zero extended*/*zero tailed* immediate.