* `andc $mDst0, $mSrc0, $mSrc1`
* `andc $mDst0, $mSrc0, zimm12`
* `andc $aDst0, $aSrc0, $aSrc1`
* `andc $aDst0, $aSrc0, zimm12`
* `andc $aDst0, $aSrc0, immz12`

Bitwise logical AND of first source register value with the bitwise
negated value of a second source register value or *zero extended*/*zero
tailed* immediate.