# and $mDst0 $mSrc0 $mSrc1

32-bit bitwise logical AND


## $mDst0

## $mSrc0

## $mSrc1

# and $mDst0 $mSrc0 zimm12

32-bit bitwise logical AND


## $mDst0

## $mSrc0

## zimm12

# and $aDst0 $aSrc0 $aSrc1

32-bit bitwise logical AND


## $aDst0

## $aSrc0

## $aSrc1

# and $aDst0 $aSrc0 zimm12

32-bit bitwise logical AND


## $aDst0

## $aSrc0

## zimm12

# and $aDst0 $aSrc0 immz12

32-bit bitwise logical AND


## $aDst0

## $aSrc0

## immz12