# f16v4cmpne $aDst0:Dst0+1 $aSrc0:Src0+1 $aSrc1:Src1+1

*Half-precision* vector inequality test


## $aDst0:Dst0+1

## $aSrc0:Src0+1

## $aSrc1:Src1+1

# f16v4cmpne $aDst0:Dst0+1 $aSrc0:BL $aSrc1:Src1+1

*Half-precision* vector inequality test


## $aDst0:Dst0+1

## $aSrc0:BL

## $aSrc1:Src1+1

# f16v4cmpne $aDst0:Dst0+1 $aSrc0:BU $aSrc1:Src1+1

*Half-precision* vector inequality test


## $aDst0:Dst0+1

## $aSrc0:BU

## $aSrc1:Src1+1