/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace Colossus {
  enum {
    PHI	= 0,
    INLINEASM	= 1,
    INLINEASM_BR	= 2,
    CFI_INSTRUCTION	= 3,
    EH_LABEL	= 4,
    GC_LABEL	= 5,
    ANNOTATION_LABEL	= 6,
    KILL	= 7,
    EXTRACT_SUBREG	= 8,
    INSERT_SUBREG	= 9,
    IMPLICIT_DEF	= 10,
    INIT_UNDEF	= 11,
    SUBREG_TO_REG	= 12,
    COPY_TO_REGCLASS	= 13,
    DBG_VALUE	= 14,
    DBG_VALUE_LIST	= 15,
    DBG_INSTR_REF	= 16,
    DBG_PHI	= 17,
    DBG_LABEL	= 18,
    REG_SEQUENCE	= 19,
    COPY	= 20,
    BUNDLE	= 21,
    LIFETIME_START	= 22,
    LIFETIME_END	= 23,
    PSEUDO_PROBE	= 24,
    ARITH_FENCE	= 25,
    STACKMAP	= 26,
    FENTRY_CALL	= 27,
    PATCHPOINT	= 28,
    LOAD_STACK_GUARD	= 29,
    PREALLOCATED_SETUP	= 30,
    PREALLOCATED_ARG	= 31,
    STATEPOINT	= 32,
    LOCAL_ESCAPE	= 33,
    FAULTING_OP	= 34,
    PATCHABLE_OP	= 35,
    PATCHABLE_FUNCTION_ENTER	= 36,
    PATCHABLE_RET	= 37,
    PATCHABLE_FUNCTION_EXIT	= 38,
    PATCHABLE_TAIL_CALL	= 39,
    PATCHABLE_EVENT_CALL	= 40,
    PATCHABLE_TYPED_EVENT_CALL	= 41,
    ICALL_BRANCH_FUNNEL	= 42,
    FAKE_USE	= 43,
    MEMBARRIER	= 44,
    JUMP_TABLE_DEBUG_INFO	= 45,
    CONVERGENCECTRL_ENTRY	= 46,
    CONVERGENCECTRL_ANCHOR	= 47,
    CONVERGENCECTRL_LOOP	= 48,
    CONVERGENCECTRL_GLUE	= 49,
    G_ASSERT_SEXT	= 50,
    G_ASSERT_ZEXT	= 51,
    G_ASSERT_ALIGN	= 52,
    G_ADD	= 53,
    G_SUB	= 54,
    G_MUL	= 55,
    G_SDIV	= 56,
    G_UDIV	= 57,
    G_SREM	= 58,
    G_UREM	= 59,
    G_SDIVREM	= 60,
    G_UDIVREM	= 61,
    G_AND	= 62,
    G_OR	= 63,
    G_XOR	= 64,
    G_ABDS	= 65,
    G_ABDU	= 66,
    G_IMPLICIT_DEF	= 67,
    G_PHI	= 68,
    G_FRAME_INDEX	= 69,
    G_GLOBAL_VALUE	= 70,
    G_PTRAUTH_GLOBAL_VALUE	= 71,
    G_CONSTANT_POOL	= 72,
    G_EXTRACT	= 73,
    G_UNMERGE_VALUES	= 74,
    G_INSERT	= 75,
    G_MERGE_VALUES	= 76,
    G_BUILD_VECTOR	= 77,
    G_BUILD_VECTOR_TRUNC	= 78,
    G_CONCAT_VECTORS	= 79,
    G_PTRTOINT	= 80,
    G_INTTOPTR	= 81,
    G_BITCAST	= 82,
    G_FREEZE	= 83,
    G_CONSTANT_FOLD_BARRIER	= 84,
    G_INTRINSIC_FPTRUNC_ROUND	= 85,
    G_INTRINSIC_TRUNC	= 86,
    G_INTRINSIC_ROUND	= 87,
    G_INTRINSIC_LRINT	= 88,
    G_INTRINSIC_LLRINT	= 89,
    G_INTRINSIC_ROUNDEVEN	= 90,
    G_READCYCLECOUNTER	= 91,
    G_READSTEADYCOUNTER	= 92,
    G_LOAD	= 93,
    G_SEXTLOAD	= 94,
    G_ZEXTLOAD	= 95,
    G_INDEXED_LOAD	= 96,
    G_INDEXED_SEXTLOAD	= 97,
    G_INDEXED_ZEXTLOAD	= 98,
    G_STORE	= 99,
    G_INDEXED_STORE	= 100,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 101,
    G_ATOMIC_CMPXCHG	= 102,
    G_ATOMICRMW_XCHG	= 103,
    G_ATOMICRMW_ADD	= 104,
    G_ATOMICRMW_SUB	= 105,
    G_ATOMICRMW_AND	= 106,
    G_ATOMICRMW_NAND	= 107,
    G_ATOMICRMW_OR	= 108,
    G_ATOMICRMW_XOR	= 109,
    G_ATOMICRMW_MAX	= 110,
    G_ATOMICRMW_MIN	= 111,
    G_ATOMICRMW_UMAX	= 112,
    G_ATOMICRMW_UMIN	= 113,
    G_ATOMICRMW_FADD	= 114,
    G_ATOMICRMW_FSUB	= 115,
    G_ATOMICRMW_FMAX	= 116,
    G_ATOMICRMW_FMIN	= 117,
    G_ATOMICRMW_UINC_WRAP	= 118,
    G_ATOMICRMW_UDEC_WRAP	= 119,
    G_ATOMICRMW_USUB_COND	= 120,
    G_ATOMICRMW_USUB_SAT	= 121,
    G_FENCE	= 122,
    G_PREFETCH	= 123,
    G_BRCOND	= 124,
    G_BRINDIRECT	= 125,
    G_INVOKE_REGION_START	= 126,
    G_INTRINSIC	= 127,
    G_INTRINSIC_W_SIDE_EFFECTS	= 128,
    G_INTRINSIC_CONVERGENT	= 129,
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS	= 130,
    G_ANYEXT	= 131,
    G_TRUNC	= 132,
    G_CONSTANT	= 133,
    G_FCONSTANT	= 134,
    G_VASTART	= 135,
    G_VAARG	= 136,
    G_SEXT	= 137,
    G_SEXT_INREG	= 138,
    G_ZEXT	= 139,
    G_SHL	= 140,
    G_LSHR	= 141,
    G_ASHR	= 142,
    G_FSHL	= 143,
    G_FSHR	= 144,
    G_ROTR	= 145,
    G_ROTL	= 146,
    G_ICMP	= 147,
    G_FCMP	= 148,
    G_SCMP	= 149,
    G_UCMP	= 150,
    G_SELECT	= 151,
    G_UADDO	= 152,
    G_UADDE	= 153,
    G_USUBO	= 154,
    G_USUBE	= 155,
    G_SADDO	= 156,
    G_SADDE	= 157,
    G_SSUBO	= 158,
    G_SSUBE	= 159,
    G_UMULO	= 160,
    G_SMULO	= 161,
    G_UMULH	= 162,
    G_SMULH	= 163,
    G_UADDSAT	= 164,
    G_SADDSAT	= 165,
    G_USUBSAT	= 166,
    G_SSUBSAT	= 167,
    G_USHLSAT	= 168,
    G_SSHLSAT	= 169,
    G_SMULFIX	= 170,
    G_UMULFIX	= 171,
    G_SMULFIXSAT	= 172,
    G_UMULFIXSAT	= 173,
    G_SDIVFIX	= 174,
    G_UDIVFIX	= 175,
    G_SDIVFIXSAT	= 176,
    G_UDIVFIXSAT	= 177,
    G_FADD	= 178,
    G_FSUB	= 179,
    G_FMUL	= 180,
    G_FMA	= 181,
    G_FMAD	= 182,
    G_FDIV	= 183,
    G_FREM	= 184,
    G_FPOW	= 185,
    G_FPOWI	= 186,
    G_FEXP	= 187,
    G_FEXP2	= 188,
    G_FEXP10	= 189,
    G_FLOG	= 190,
    G_FLOG2	= 191,
    G_FLOG10	= 192,
    G_FLDEXP	= 193,
    G_FFREXP	= 194,
    G_FNEG	= 195,
    G_FPEXT	= 196,
    G_FPTRUNC	= 197,
    G_FPTOSI	= 198,
    G_FPTOUI	= 199,
    G_SITOFP	= 200,
    G_UITOFP	= 201,
    G_FPTOSI_SAT	= 202,
    G_FPTOUI_SAT	= 203,
    G_FABS	= 204,
    G_FCOPYSIGN	= 205,
    G_IS_FPCLASS	= 206,
    G_FCANONICALIZE	= 207,
    G_FMINNUM	= 208,
    G_FMAXNUM	= 209,
    G_FMINNUM_IEEE	= 210,
    G_FMAXNUM_IEEE	= 211,
    G_FMINIMUM	= 212,
    G_FMAXIMUM	= 213,
    G_GET_FPENV	= 214,
    G_SET_FPENV	= 215,
    G_RESET_FPENV	= 216,
    G_GET_FPMODE	= 217,
    G_SET_FPMODE	= 218,
    G_RESET_FPMODE	= 219,
    G_PTR_ADD	= 220,
    G_PTRMASK	= 221,
    G_SMIN	= 222,
    G_SMAX	= 223,
    G_UMIN	= 224,
    G_UMAX	= 225,
    G_ABS	= 226,
    G_LROUND	= 227,
    G_LLROUND	= 228,
    G_BR	= 229,
    G_BRJT	= 230,
    G_VSCALE	= 231,
    G_INSERT_SUBVECTOR	= 232,
    G_EXTRACT_SUBVECTOR	= 233,
    G_INSERT_VECTOR_ELT	= 234,
    G_EXTRACT_VECTOR_ELT	= 235,
    G_SHUFFLE_VECTOR	= 236,
    G_SPLAT_VECTOR	= 237,
    G_STEP_VECTOR	= 238,
    G_VECTOR_COMPRESS	= 239,
    G_CTTZ	= 240,
    G_CTTZ_ZERO_UNDEF	= 241,
    G_CTLZ	= 242,
    G_CTLZ_ZERO_UNDEF	= 243,
    G_CTPOP	= 244,
    G_BSWAP	= 245,
    G_BITREVERSE	= 246,
    G_FCEIL	= 247,
    G_FCOS	= 248,
    G_FSIN	= 249,
    G_FSINCOS	= 250,
    G_FTAN	= 251,
    G_FACOS	= 252,
    G_FASIN	= 253,
    G_FATAN	= 254,
    G_FATAN2	= 255,
    G_FCOSH	= 256,
    G_FSINH	= 257,
    G_FTANH	= 258,
    G_FSQRT	= 259,
    G_FFLOOR	= 260,
    G_FRINT	= 261,
    G_FNEARBYINT	= 262,
    G_ADDRSPACE_CAST	= 263,
    G_BLOCK_ADDR	= 264,
    G_JUMP_TABLE	= 265,
    G_DYN_STACKALLOC	= 266,
    G_STACKSAVE	= 267,
    G_STACKRESTORE	= 268,
    G_STRICT_FADD	= 269,
    G_STRICT_FSUB	= 270,
    G_STRICT_FMUL	= 271,
    G_STRICT_FDIV	= 272,
    G_STRICT_FREM	= 273,
    G_STRICT_FMA	= 274,
    G_STRICT_FSQRT	= 275,
    G_STRICT_FLDEXP	= 276,
    G_READ_REGISTER	= 277,
    G_WRITE_REGISTER	= 278,
    G_MEMCPY	= 279,
    G_MEMCPY_INLINE	= 280,
    G_MEMMOVE	= 281,
    G_MEMSET	= 282,
    G_BZERO	= 283,
    G_TRAP	= 284,
    G_DEBUGTRAP	= 285,
    G_UBSANTRAP	= 286,
    G_VECREDUCE_SEQ_FADD	= 287,
    G_VECREDUCE_SEQ_FMUL	= 288,
    G_VECREDUCE_FADD	= 289,
    G_VECREDUCE_FMUL	= 290,
    G_VECREDUCE_FMAX	= 291,
    G_VECREDUCE_FMIN	= 292,
    G_VECREDUCE_FMAXIMUM	= 293,
    G_VECREDUCE_FMINIMUM	= 294,
    G_VECREDUCE_ADD	= 295,
    G_VECREDUCE_MUL	= 296,
    G_VECREDUCE_AND	= 297,
    G_VECREDUCE_OR	= 298,
    G_VECREDUCE_XOR	= 299,
    G_VECREDUCE_SMAX	= 300,
    G_VECREDUCE_SMIN	= 301,
    G_VECREDUCE_UMAX	= 302,
    G_VECREDUCE_UMIN	= 303,
    G_SBFX	= 304,
    G_UBFX	= 305,
    ADJCALLSTACKDOWN	= 306,
    ADJCALLSTACKUP	= 307,
    CALLIND	= 308,
    CALL_PSEUDO	= 309,
    CLOOP_BEGIN_TERMINATOR	= 310,
    CLOOP_BEGIN_VALUE	= 311,
    CLOOP_END_BRANCH	= 312,
    CLOOP_END_VALUE	= 313,
    CLOOP_GUARD_BRANCH	= 314,
    FRAME_INDEX	= 315,
    FRAME_TO_ARGS_OFFSET	= 316,
    ICALL	= 317,
    LABEL	= 318,
    LD32_ACC_FI	= 319,
    LD32_A_FI	= 320,
    LD32_FI	= 321,
    LD64_ACC_FI	= 322,
    LD64_A_FI	= 323,
    LD64_FI	= 324,
    LDCONST	= 325,
    LDCONST_A	= 326,
    LDS16_FI	= 327,
    LDS8_FI	= 328,
    LDZ16_A_FI	= 329,
    LDZ16_FI	= 330,
    LDZ8_FI	= 331,
    MEM_BARRIER	= 332,
    RTN_PSEUDO	= 333,
    RTN_REG_HOLDER	= 334,
    SELECT_F16	= 335,
    SELECT_F32	= 336,
    SELECT_V2F16	= 337,
    SELECT_V2F32	= 338,
    SELECT_V4F16	= 339,
    SETLR	= 340,
    ST32_ACC_FI	= 341,
    ST32_A_FI	= 342,
    ST32_FI	= 343,
    ST64_ACC_FI	= 344,
    ST64_A_FI	= 345,
    ST64_FI	= 346,
    STACKRESTORE	= 347,
    STACKSAVE	= 348,
    SUB_IMM	= 349,
    ABS	= 350,
    ADD	= 351,
    ADD_SI	= 352,
    ADD_ZI	= 353,
    AND	= 354,
    AND64	= 355,
    ANDC	= 356,
    ANDC64	= 357,
    ANDC_A	= 358,
    ANDC_IZ_A	= 359,
    ANDC_ZI	= 360,
    ANDC_ZI_A	= 361,
    AND_A	= 362,
    AND_IZ_A	= 363,
    AND_ZI	= 364,
    AND_ZI_A	= 365,
    ATOM	= 366,
    BITREV8	= 367,
    BR	= 368,
    BRIND	= 369,
    BRNEG	= 370,
    BRNZ	= 371,
    BRNZDEC	= 372,
    BRPOS	= 373,
    BRZ	= 374,
    CALL	= 375,
    CLZ	= 376,
    CMPEQ	= 377,
    CMPEQ_SI	= 378,
    CMPEQ_ZI	= 379,
    CMPNE	= 380,
    CMPSLT	= 381,
    CMPSLT_SI	= 382,
    CMPULT	= 383,
    CMPULT_ZI	= 384,
    CMS	= 385,
    EXITNEG	= 386,
    EXITNZ	= 387,
    EXITPOS	= 388,
    EXITZ	= 389,
    F16TOF32	= 390,
    F16V2ABSADD	= 391,
    F16V2ABSMAX	= 392,
    F16V2ADD	= 393,
    F16V2ADD_BL	= 394,
    F16V2ADD_BU	= 395,
    F16V2CLAMP	= 396,
    F16V2CLASS	= 397,
    F16V2CMAC	= 398,
    F16V2CMPEQ	= 399,
    F16V2CMPEQ_BL	= 400,
    F16V2CMPEQ_BU	= 401,
    F16V2CMPGE	= 402,
    F16V2CMPGE_BL	= 403,
    F16V2CMPGE_BU	= 404,
    F16V2CMPGT	= 405,
    F16V2CMPGT_BL	= 406,
    F16V2CMPGT_BU	= 407,
    F16V2CMPLE	= 408,
    F16V2CMPLE_BL	= 409,
    F16V2CMPLE_BU	= 410,
    F16V2CMPLT	= 411,
    F16V2CMPLT_BL	= 412,
    F16V2CMPLT_BU	= 413,
    F16V2CMPNE	= 414,
    F16V2CMPNE_BL	= 415,
    F16V2CMPNE_BU	= 416,
    F16V2EXP	= 417,
    F16V2EXP2	= 418,
    F16V2GINA	= 419,
    F16V2GRAND	= 420,
    F16V2LN	= 421,
    F16V2LOG2	= 422,
    F16V2MAX	= 423,
    F16V2MAXC	= 424,
    F16V2MIN	= 425,
    F16V2MUL	= 426,
    F16V2MUL_BL	= 427,
    F16V2MUL_BU	= 428,
    F16V2SIGMOID	= 429,
    F16V2SUB	= 430,
    F16V2SUB_BL	= 431,
    F16V2SUB_BU	= 432,
    F16V2SUFROMUI	= 433,
    F16V2SUM	= 434,
    F16V2TANH	= 435,
    F16V2TOF32	= 436,
    F16V2TOF8	= 437,
    F16V4ABSACC	= 438,
    F16V4ABSADD	= 439,
    F16V4ABSMAX	= 440,
    F16V4ACC	= 441,
    F16V4ADD	= 442,
    F16V4ADD_BL	= 443,
    F16V4ADD_BU	= 444,
    F16V4CLAMP	= 445,
    F16V4CLASS	= 446,
    F16V4CMAC	= 447,
    F16V4CMPEQ	= 448,
    F16V4CMPEQ_BL	= 449,
    F16V4CMPEQ_BU	= 450,
    F16V4CMPGE	= 451,
    F16V4CMPGE_BL	= 452,
    F16V4CMPGE_BU	= 453,
    F16V4CMPGT	= 454,
    F16V4CMPGT_BL	= 455,
    F16V4CMPGT_BU	= 456,
    F16V4CMPLE	= 457,
    F16V4CMPLE_BL	= 458,
    F16V4CMPLE_BU	= 459,
    F16V4CMPLT	= 460,
    F16V4CMPLT_BL	= 461,
    F16V4CMPLT_BU	= 462,
    F16V4CMPNE	= 463,
    F16V4CMPNE_BL	= 464,
    F16V4CMPNE_BU	= 465,
    F16V4GACC	= 466,
    F16V4HIHOAMP	= 467,
    F16V4HIHOSLIC	= 468,
    F16V4HIHOV4AMP	= 469,
    F16V4HIHOV4SLIC	= 470,
    F16V4ISTACC	= 471,
    F16V4MAX	= 472,
    F16V4MAXC	= 473,
    F16V4MIN	= 474,
    F16V4MIX	= 475,
    F16V4MUL	= 476,
    F16V4MUL_BL	= 477,
    F16V4MUL_BU	= 478,
    F16V4RMASK	= 479,
    F16V4SIHOAMP	= 480,
    F16V4SIHOSLIC	= 481,
    F16V4SISOAMP	= 482,
    F16V4SISOSLIC	= 483,
    F16V4STACC	= 484,
    F16V4SUB	= 485,
    F16V4SUB_BL	= 486,
    F16V4SUB_BU	= 487,
    F16V4SUFROMUI	= 488,
    F16V4SUM	= 489,
    F16V8ABSACC	= 490,
    F16V8ACC	= 491,
    F16V8SQACC	= 492,
    F16V8TOF8	= 493,
    F32ABSADD	= 494,
    F32ABSMAX	= 495,
    F32ADD	= 496,
    F32CLAMP	= 497,
    F32CLASS	= 498,
    F32CMPEQ	= 499,
    F32CMPGE	= 500,
    F32CMPGT	= 501,
    F32CMPLE	= 502,
    F32CMPLT	= 503,
    F32CMPNE	= 504,
    F32DIV	= 505,
    F32EXP	= 506,
    F32EXP2	= 507,
    F32FROMI32	= 508,
    F32FROMUI32	= 509,
    F32INT	= 510,
    F32LN	= 511,
    F32LOG2	= 512,
    F32MAC	= 513,
    F32MAX	= 514,
    F32MIN	= 515,
    F32MUL	= 516,
    F32OORX	= 517,
    F32OOX	= 518,
    F32SIGMOID	= 519,
    F32SISOAMP	= 520,
    F32SISOSLIC	= 521,
    F32SISOV2AMP	= 522,
    F32SQRT	= 523,
    F32SUB	= 524,
    F32SUFROMUI	= 525,
    F32TANH	= 526,
    F32TOF16	= 527,
    F32TOI32	= 528,
    F32TOUI32	= 529,
    F32V2ABSADD	= 530,
    F32V2ABSMAX	= 531,
    F32V2ADD	= 532,
    F32V2ADD_BL	= 533,
    F32V2AOP	= 534,
    F32V2AXPY	= 535,
    F32V2CLAMP	= 536,
    F32V2CLASS	= 537,
    F32V2CMPEQ	= 538,
    F32V2CMPEQ_BL	= 539,
    F32V2CMPGE	= 540,
    F32V2CMPGE_BL	= 541,
    F32V2CMPGT	= 542,
    F32V2CMPGT_BL	= 543,
    F32V2CMPLE	= 544,
    F32V2CMPLE_BL	= 545,
    F32V2CMPLT	= 546,
    F32V2CMPLT_BL	= 547,
    F32V2CMPNE	= 548,
    F32V2CMPNE_BL	= 549,
    F32V2GINA	= 550,
    F32V2GRAND	= 551,
    F32V2MAC	= 552,
    F32V2MAX	= 553,
    F32V2MIN	= 554,
    F32V2MUL	= 555,
    F32V2MUL_BL	= 556,
    F32V2RMASK	= 557,
    F32V2SUB	= 558,
    F32V2SUB_BL	= 559,
    F32V2SUFROMUI	= 560,
    F32V2TOF16	= 561,
    F32V4ABSACC	= 562,
    F32V4ACC	= 563,
    F32V4SQACC	= 564,
    F32V4TOF16	= 565,
    F8V2TOF16	= 566,
    F8V4CLASS	= 567,
    F8V4TOF16	= 568,
    F8V8HIHOV4AMP	= 569,
    F8V8HIHOV4SLIC	= 570,
    GET	= 571,
    LD128	= 572,
    LD128PUTCS	= 573,
    LD128STEP	= 574,
    LD128STEP_SI	= 575,
    LD128_ZI	= 576,
    LD2X64PACE	= 577,
    LD2XST64PACE	= 578,
    LD32	= 579,
    LD32STEP	= 580,
    LD32STEP_A	= 581,
    LD32STEP_SI	= 582,
    LD32STEP_SI_A	= 583,
    LD32_A	= 584,
    LD32_ZI	= 585,
    LD32_ZI_A	= 586,
    LD64A32	= 587,
    LD64A32PACE	= 588,
    LD64B16PACE	= 589,
    LD64PUTCS	= 590,
    LD64STEP_A	= 591,
    LD64STEP_SI_A	= 592,
    LD64_A	= 593,
    LD64_ZI_A	= 594,
    LDB16	= 595,
    LDB16B16	= 596,
    LDB16STEP	= 597,
    LDB16STEP_SI	= 598,
    LDB16_ZI	= 599,
    LDB8	= 600,
    LDB8_ZI	= 601,
    LDD16A32	= 602,
    LDD16A64	= 603,
    LDD16B16	= 604,
    LDD16V2A32	= 605,
    LDS16	= 606,
    LDS16STEP	= 607,
    LDS16STEP_SI	= 608,
    LDS16_ZI	= 609,
    LDS8	= 610,
    LDS8STEP	= 611,
    LDS8STEP_SI	= 612,
    LDS8_ZI	= 613,
    LDST64PACE	= 614,
    LDZ16	= 615,
    LDZ16STEP	= 616,
    LDZ16STEP_SI	= 617,
    LDZ16_ZI	= 618,
    LDZ8	= 619,
    LDZ8STEP	= 620,
    LDZ8STEP_SI	= 621,
    LDZ8_ZI	= 622,
    MAX	= 623,
    MAX_SI	= 624,
    MAX_ZI	= 625,
    MIN	= 626,
    MIN_SI	= 627,
    MIN_ZI	= 628,
    MOVZ	= 629,
    MUL	= 630,
    MUL_SI	= 631,
    NOT	= 632,
    NOT64	= 633,
    OR	= 634,
    OR64	= 635,
    OR_A	= 636,
    OR_IZ	= 637,
    OR_IZ_A	= 638,
    OR_ZI	= 639,
    OR_ZI_A	= 640,
    POPC	= 641,
    PUT	= 642,
    ROLL16	= 643,
    ROLL16_A	= 644,
    ROLL32	= 645,
    ROLL8L	= 646,
    ROLL8L_1	= 647,
    ROLL8R	= 648,
    ROLL8R_1	= 649,
    RPT	= 650,
    RPT_ZI	= 651,
    RTN	= 652,
    RUN	= 653,
    RUNALL	= 654,
    SETZI	= 655,
    SETZI_A	= 656,
    SHL	= 657,
    SHL_ZI	= 658,
    SHR	= 659,
    SHRS	= 660,
    SHRS_ZI	= 661,
    SHR_ZI	= 662,
    SHUF8X8HI	= 663,
    SHUF8X8HI_1	= 664,
    SHUF8X8LO	= 665,
    SHUF8X8LO_1	= 666,
    SORT4X16HI	= 667,
    SORT4X16HI_A	= 668,
    SORT4X16LO	= 669,
    SORT4X16LO_A	= 670,
    SORT4X16LO_BU	= 671,
    SORT4X32HI	= 672,
    SORT4X32LO	= 673,
    SORT8	= 674,
    SORT8X8HI	= 675,
    SORT8X8HI_1	= 676,
    SORT8X8LO	= 677,
    SORT8X8LO_1	= 678,
    SORT8_1	= 679,
    ST32STEP_A	= 680,
    ST32STEP_SI	= 681,
    ST32STEP_SI_A	= 682,
    ST32_A	= 683,
    ST32_ZI	= 684,
    ST32_ZI_A	= 685,
    ST64PACE	= 686,
    ST64STEP_A	= 687,
    ST64STEP_SI_A	= 688,
    ST64_A	= 689,
    ST64_ZI_A	= 690,
    STM32	= 691,
    STM32STEP	= 692,
    SUB	= 693,
    SUB_SI	= 694,
    SUB_ZI	= 695,
    SWAP8	= 696,
    SWAP8_1	= 697,
    TAPACK	= 698,
    TRAP	= 699,
    UGET	= 700,
    UPUT	= 701,
    URAND32	= 702,
    URAND64	= 703,
    XNOR	= 704,
    XOR	= 705,
    INSTRUCTION_LIST_END = 706
  };

} // end namespace Colossus
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace Colossus {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    WriteMain	= 1,
    WriteAux	= 2,
    WriteMain_WriteFreeMain	= 3,
    WriteMain_WriteFreeMain_WriteFreeMain	= 4,
    COPY	= 5,
    SCHED_LIST_END = 6
  };
} // end namespace Sched
} // end namespace Colossus
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct ColossusInstrTable {
  MCInstrDesc Insts[706];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[467];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[3];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned ColossusImpOpBase = sizeof ColossusInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const ColossusInstrTable ColossusDescs = {
  {
    { 705,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #705 = XOR
    { 704,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #704 = XNOR
    { 703,	2,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	229,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #703 = URAND64
    { 702,	2,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	224,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #702 = URAND32
    { 701,	3,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	419,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x3400000ULL },  // Inst #701 = UPUT
    { 700,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	419,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x3400000ULL },  // Inst #700 = UGET
    { 699,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	13,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x3000000ULL },  // Inst #699 = TRAP
    { 698,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	462,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #698 = TAPACK
    { 697,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #697 = SWAP8_1
    { 696,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	195,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #696 = SWAP8
    { 695,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #695 = SUB_ZI
    { 694,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #694 = SUB_SI
    { 693,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #693 = SUB
    { 692,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	411,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #692 = STM32STEP
    { 691,	4,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	458,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #691 = STM32
    { 690,	5,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	385,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #690 = ST64_ZI_A
    { 689,	5,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	380,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #689 = ST64_A
    { 688,	6,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	452,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000082ULL },  // Inst #688 = ST64STEP_SI_A
    { 687,	6,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	446,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000082ULL },  // Inst #687 = ST64STEP_A
    { 686,	6,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	440,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000082ULL },  // Inst #686 = ST64PACE
    { 685,	5,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	356,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #685 = ST32_ZI_A
    { 684,	5,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	351,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #684 = ST32_ZI
    { 683,	5,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	346,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #683 = ST32_A
    { 682,	6,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	434,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000082ULL },  // Inst #682 = ST32STEP_SI_A
    { 681,	6,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	428,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000082ULL },  // Inst #681 = ST32STEP_SI
    { 680,	6,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	422,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000082ULL },  // Inst #680 = ST32STEP_A
    { 679,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #679 = SORT8_1
    { 678,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #678 = SORT8X8LO_1
    { 677,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #677 = SORT8X8LO
    { 676,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #676 = SORT8X8HI_1
    { 675,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #675 = SORT8X8HI
    { 674,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	195,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #674 = SORT8
    { 673,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #673 = SORT4X32LO
    { 672,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #672 = SORT4X32HI
    { 671,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #671 = SORT4X16LO_BU
    { 670,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #670 = SORT4X16LO_A
    { 669,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #669 = SORT4X16LO
    { 668,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #668 = SORT4X16HI_A
    { 667,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #667 = SORT4X16HI
    { 666,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #666 = SHUF8X8LO_1
    { 665,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #665 = SHUF8X8LO
    { 664,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #664 = SHUF8X8HI_1
    { 663,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #663 = SHUF8X8HI
    { 662,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #662 = SHR_ZI
    { 661,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #661 = SHRS_ZI
    { 660,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #660 = SHRS
    { 659,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #659 = SHR
    { 658,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #658 = SHL_ZI
    { 657,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #657 = SHL
    { 656,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	419,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #656 = SETZI_A
    { 655,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #655 = SETZI
    { 654,	4,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1000000ULL },  // Inst #654 = RUNALL
    { 653,	4,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x1000000ULL },  // Inst #653 = RUN
    { 652,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #652 = RTN
    { 651,	3,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	416,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #651 = RPT_ZI
    { 650,	3,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #650 = RPT
    { 649,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #649 = ROLL8R_1
    { 648,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #648 = ROLL8R
    { 647,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #647 = ROLL8L_1
    { 646,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #646 = ROLL8L
    { 645,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #645 = ROLL32
    { 644,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #644 = ROLL16_A
    { 643,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #643 = ROLL16
    { 642,	3,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x3000000ULL },  // Inst #642 = PUT
    { 641,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	195,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #641 = POPC
    { 640,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #640 = OR_ZI_A
    { 639,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #639 = OR_ZI
    { 638,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #638 = OR_IZ_A
    { 637,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #637 = OR_IZ
    { 636,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #636 = OR_A
    { 635,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #635 = OR64
    { 634,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #634 = OR
    { 633,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	242,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #633 = NOT64
    { 632,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #632 = NOT
    { 631,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #631 = MUL_SI
    { 630,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #630 = MUL
    { 629,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	411,	0|(1ULL<<MCID::Select)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #629 = MOVZ
    { 628,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #628 = MIN_ZI
    { 627,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #627 = MIN_SI
    { 626,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #626 = MIN
    { 625,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #625 = MAX_ZI
    { 624,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #624 = MAX_SI
    { 623,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #623 = MAX
    { 622,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	351,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #622 = LDZ8_ZI
    { 621,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	334,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #621 = LDZ8STEP_SI
    { 620,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	322,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #620 = LDZ8STEP
    { 619,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	317,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #619 = LDZ8
    { 618,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	351,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #618 = LDZ16_ZI
    { 617,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	334,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #617 = LDZ16STEP_SI
    { 616,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	322,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #616 = LDZ16STEP
    { 615,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	317,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #615 = LDZ16
    { 614,	7,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	404,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #614 = LDST64PACE
    { 613,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	351,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #613 = LDS8_ZI
    { 612,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	334,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #612 = LDS8STEP_SI
    { 611,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	322,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #611 = LDS8STEP
    { 610,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	317,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #610 = LDS8
    { 609,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	351,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #609 = LDS16_ZI
    { 608,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	334,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #608 = LDS16STEP_SI
    { 607,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	322,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #607 = LDS16STEP
    { 606,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	317,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #606 = LDS16
    { 605,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	397,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2021021ULL },  // Inst #605 = LDD16V2A32
    { 604,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	397,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2021021ULL },  // Inst #604 = LDD16B16
    { 603,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	390,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2021021ULL },  // Inst #603 = LDD16A64
    { 602,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	397,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2021021ULL },  // Inst #602 = LDD16A32
    { 601,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	356,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #601 = LDB8_ZI
    { 600,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	346,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #600 = LDB8
    { 599,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	356,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #599 = LDB16_ZI
    { 598,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	340,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #598 = LDB16STEP_SI
    { 597,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	328,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #597 = LDB16STEP
    { 596,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	390,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x200b00bULL },  // Inst #596 = LDB16B16
    { 595,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	346,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #595 = LDB16
    { 594,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	385,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #594 = LD64_ZI_A
    { 593,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	380,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #593 = LD64_A
    { 592,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	374,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #592 = LD64STEP_SI_A
    { 591,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	368,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #591 = LD64STEP_A
    { 590,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	13,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #590 = LD64PUTCS
    { 589,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	361,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2002002ULL },  // Inst #589 = LD64B16PACE
    { 588,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	361,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2002002ULL },  // Inst #588 = LD64A32PACE
    { 587,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	286,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000201ULL },  // Inst #587 = LD64A32
    { 586,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	356,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #586 = LD32_ZI_A
    { 585,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	351,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #585 = LD32_ZI
    { 584,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	346,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #584 = LD32_A
    { 583,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	340,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #583 = LD32STEP_SI_A
    { 582,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	334,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #582 = LD32STEP_SI
    { 581,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	328,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #581 = LD32STEP_A
    { 580,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	322,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #580 = LD32STEP
    { 579,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	317,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #579 = LD32
    { 578,	7,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	310,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #578 = LD2XST64PACE
    { 577,	7,	3,	4,	4,	0,	0,	ColossusImpOpBase + 0,	303,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2002002ULL },  // Inst #577 = LD2X64PACE
    { 576,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	298,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #576 = LD128_ZI
    { 575,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	292,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #575 = LD128STEP_SI
    { 574,	6,	2,	4,	3,	0,	0,	ColossusImpOpBase + 0,	286,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000402ULL },  // Inst #574 = LD128STEP
    { 573,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	13,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #573 = LD128PUTCS
    { 572,	5,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	281,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #572 = LD128
    { 571,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x3000000ULL },  // Inst #571 = GET
    { 570,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	250,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #570 = F8V8HIHOV4SLIC
    { 569,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	250,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #569 = F8V8HIHOV4AMP
    { 568,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	226,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #568 = F8V4TOF16
    { 567,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #567 = F8V4CLASS
    { 566,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #566 = F8V2TOF16
    { 565,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	265,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #565 = F32V4TOF16
    { 564,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	263,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #564 = F32V4SQACC
    { 563,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	263,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #563 = F32V4ACC
    { 562,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	263,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #562 = F32V4ABSACC
    { 561,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	239,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #561 = F32V2TOF16
    { 560,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	242,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #560 = F32V2SUFROMUI
    { 559,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #559 = F32V2SUB_BL
    { 558,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #558 = F32V2SUB
    { 557,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	235,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #557 = F32V2RMASK
    { 556,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #556 = F32V2MUL_BL
    { 555,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #555 = F32V2MUL
    { 554,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #554 = F32V2MIN
    { 553,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #553 = F32V2MAX
    { 552,	3,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	242,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #552 = F32V2MAC
    { 551,	2,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	229,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #551 = F32V2GRAND
    { 550,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	277,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #550 = F32V2GINA
    { 549,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #549 = F32V2CMPNE_BL
    { 548,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #548 = F32V2CMPNE
    { 547,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #547 = F32V2CMPLT_BL
    { 546,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #546 = F32V2CMPLT
    { 545,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #545 = F32V2CMPLE_BL
    { 544,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #544 = F32V2CMPLE
    { 543,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #543 = F32V2CMPGT_BL
    { 542,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #542 = F32V2CMPGT
    { 541,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #541 = F32V2CMPGE_BL
    { 540,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #540 = F32V2CMPGE
    { 539,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #539 = F32V2CMPEQ_BL
    { 538,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #538 = F32V2CMPEQ
    { 537,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #537 = F32V2CLASS
    { 536,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #536 = F32V2CLAMP
    { 535,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #535 = F32V2AXPY
    { 534,	4,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	277,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #534 = F32V2AOP
    { 533,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #533 = F32V2ADD_BL
    { 532,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #532 = F32V2ADD
    { 531,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #531 = F32V2ABSMAX
    { 530,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #530 = F32V2ABSADD
    { 529,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #529 = F32TOUI32
    { 528,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #528 = F32TOI32
    { 527,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #527 = F32TOF16
    { 526,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #526 = F32TANH
    { 525,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #525 = F32SUFROMUI
    { 524,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #524 = F32SUB
    { 523,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #523 = F32SQRT
    { 522,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	272,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #522 = F32SISOV2AMP
    { 521,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	272,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #521 = F32SISOSLIC
    { 520,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	272,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #520 = F32SISOAMP
    { 519,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #519 = F32SIGMOID
    { 518,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #518 = F32OOX
    { 517,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #517 = F32OORX
    { 516,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #516 = F32MUL
    { 515,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #515 = F32MIN
    { 514,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #514 = F32MAX
    { 513,	3,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #513 = F32MAC
    { 512,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #512 = F32LOG2
    { 511,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #511 = F32LN
    { 510,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #510 = F32INT
    { 509,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #509 = F32FROMUI32
    { 508,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #508 = F32FROMI32
    { 507,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #507 = F32EXP2
    { 506,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #506 = F32EXP
    { 505,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #505 = F32DIV
    { 504,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #504 = F32CMPNE
    { 503,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #503 = F32CMPLT
    { 502,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #502 = F32CMPLE
    { 501,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #501 = F32CMPGT
    { 500,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #500 = F32CMPGE
    { 499,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #499 = F32CMPEQ
    { 498,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #498 = F32CLASS
    { 497,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	268,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #497 = F32CLAMP
    { 496,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #496 = F32ADD
    { 495,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #495 = F32ABSMAX
    { 494,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #494 = F32ABSADD
    { 493,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	265,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #493 = F16V8TOF8
    { 492,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	263,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #492 = F16V8SQACC
    { 491,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	263,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #491 = F16V8ACC
    { 490,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	263,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #490 = F16V8ABSACC
    { 489,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	242,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #489 = F16V4SUM
    { 488,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	242,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #488 = F16V4SUFROMUI
    { 487,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #487 = F16V4SUB_BU
    { 486,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #486 = F16V4SUB_BL
    { 485,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #485 = F16V4SUB
    { 484,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	260,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #484 = F16V4STACC
    { 483,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	250,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #483 = F16V4SISOSLIC
    { 482,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	250,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #482 = F16V4SISOAMP
    { 481,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	255,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #481 = F16V4SIHOSLIC
    { 480,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	255,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #480 = F16V4SIHOAMP
    { 479,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	235,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #479 = F16V4RMASK
    { 478,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #478 = F16V4MUL_BU
    { 477,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #477 = F16V4MUL_BL
    { 476,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #476 = F16V4MUL
    { 475,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #475 = F16V4MIX
    { 474,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #474 = F16V4MIN
    { 473,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	239,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #473 = F16V4MAXC
    { 472,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #472 = F16V4MAX
    { 471,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	250,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #471 = F16V4ISTACC
    { 470,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	250,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #470 = F16V4HIHOV4SLIC
    { 469,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	250,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #469 = F16V4HIHOV4AMP
    { 468,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	245,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #468 = F16V4HIHOSLIC
    { 467,	5,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	245,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #467 = F16V4HIHOAMP
    { 466,	2,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	229,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #466 = F16V4GACC
    { 465,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #465 = F16V4CMPNE_BU
    { 464,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #464 = F16V4CMPNE_BL
    { 463,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #463 = F16V4CMPNE
    { 462,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #462 = F16V4CMPLT_BU
    { 461,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #461 = F16V4CMPLT_BL
    { 460,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #460 = F16V4CMPLT
    { 459,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #459 = F16V4CMPLE_BU
    { 458,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #458 = F16V4CMPLE_BL
    { 457,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #457 = F16V4CMPLE
    { 456,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #456 = F16V4CMPGT_BU
    { 455,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #455 = F16V4CMPGT_BL
    { 454,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #454 = F16V4CMPGT
    { 453,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #453 = F16V4CMPGE_BU
    { 452,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #452 = F16V4CMPGE_BL
    { 451,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #451 = F16V4CMPGE
    { 450,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #450 = F16V4CMPEQ_BU
    { 449,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #449 = F16V4CMPEQ_BL
    { 448,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #448 = F16V4CMPEQ
    { 447,	3,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	242,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #447 = F16V4CMAC
    { 446,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #446 = F16V4CLASS
    { 445,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	235,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #445 = F16V4CLAMP
    { 444,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #444 = F16V4ADD_BU
    { 443,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	231,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #443 = F16V4ADD_BL
    { 442,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #442 = F16V4ADD
    { 441,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	229,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #441 = F16V4ACC
    { 440,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #440 = F16V4ABSMAX
    { 439,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #439 = F16V4ABSADD
    { 438,	2,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	229,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #438 = F16V4ABSACC
    { 437,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #437 = F16V2TOF8
    { 436,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	226,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #436 = F16V2TOF32
    { 435,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #435 = F16V2TANH
    { 434,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #434 = F16V2SUM
    { 433,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #433 = F16V2SUFROMUI
    { 432,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #432 = F16V2SUB_BU
    { 431,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #431 = F16V2SUB_BL
    { 430,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #430 = F16V2SUB
    { 429,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #429 = F16V2SIGMOID
    { 428,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #428 = F16V2MUL_BU
    { 427,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #427 = F16V2MUL_BL
    { 426,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #426 = F16V2MUL
    { 425,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #425 = F16V2MIN
    { 424,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #424 = F16V2MAXC
    { 423,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #423 = F16V2MAX
    { 422,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #422 = F16V2LOG2
    { 421,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #421 = F16V2LN
    { 420,	2,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	224,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #420 = F16V2GRAND
    { 419,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #419 = F16V2GINA
    { 418,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #418 = F16V2EXP2
    { 417,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #417 = F16V2EXP
    { 416,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #416 = F16V2CMPNE_BU
    { 415,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #415 = F16V2CMPNE_BL
    { 414,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #414 = F16V2CMPNE
    { 413,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #413 = F16V2CMPLT_BU
    { 412,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #412 = F16V2CMPLT_BL
    { 411,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #411 = F16V2CMPLT
    { 410,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #410 = F16V2CMPLE_BU
    { 409,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #409 = F16V2CMPLE_BL
    { 408,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #408 = F16V2CMPLE
    { 407,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #407 = F16V2CMPGT_BU
    { 406,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #406 = F16V2CMPGT_BL
    { 405,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #405 = F16V2CMPGT
    { 404,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #404 = F16V2CMPGE_BU
    { 403,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #403 = F16V2CMPGE_BL
    { 402,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #402 = F16V2CMPGE
    { 401,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #401 = F16V2CMPEQ_BU
    { 400,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #400 = F16V2CMPEQ_BL
    { 399,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #399 = F16V2CMPEQ
    { 398,	3,	0,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #398 = F16V2CMAC
    { 397,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #397 = F16V2CLASS
    { 396,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #396 = F16V2CLAMP
    { 395,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #395 = F16V2ADD_BU
    { 394,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #394 = F16V2ADD_BL
    { 393,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #393 = F16V2ADD
    { 392,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #392 = F16V2ABSMAX
    { 391,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #391 = F16V2ABSADD
    { 390,	3,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	221,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #390 = F16TOF32
    { 389,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800000ULL },  // Inst #389 = EXITZ
    { 388,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800000ULL },  // Inst #388 = EXITPOS
    { 387,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800000ULL },  // Inst #387 = EXITNZ
    { 386,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x800000ULL },  // Inst #386 = EXITNEG
    { 385,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	195,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #385 = CMS
    { 384,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #384 = CMPULT_ZI
    { 383,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #383 = CMPULT
    { 382,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #382 = CMPSLT_SI
    { 381,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #381 = CMPSLT
    { 380,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #380 = CMPNE
    { 379,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #379 = CMPEQ_ZI
    { 378,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #378 = CMPEQ_SI
    { 377,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #377 = CMPEQ
    { 376,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	195,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #376 = CLZ
    { 375,	3,	1,	4,	1,	0,	1,	ColossusImpOpBase + 2,	157,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #375 = CALL
    { 374,	3,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #374 = BRZ
    { 373,	3,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #373 = BRPOS
    { 372,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	217,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #372 = BRNZDEC
    { 371,	3,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #371 = BRNZ
    { 370,	3,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #370 = BRNEG
    { 369,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #369 = BRIND
    { 368,	2,	0,	4,	1,	0,	0,	ColossusImpOpBase + 0,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2800000ULL },  // Inst #368 = BR
    { 367,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	195,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #367 = BITREV8
    { 366,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	214,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #366 = ATOM
    { 365,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #365 = AND_ZI_A
    { 364,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #364 = AND_ZI
    { 363,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #363 = AND_IZ_A
    { 362,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #362 = AND_A
    { 361,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #361 = ANDC_ZI_A
    { 360,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #360 = ANDC_ZI
    { 359,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #359 = ANDC_IZ_A
    { 358,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	206,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #358 = ANDC_A
    { 357,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #357 = ANDC64
    { 356,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #356 = ANDC
    { 355,	4,	1,	4,	2,	0,	0,	ColossusImpOpBase + 0,	202,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2400000ULL },  // Inst #355 = AND64
    { 354,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #354 = AND
    { 353,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #353 = ADD_ZI
    { 352,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #352 = ADD_SI
    { 351,	4,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	198,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #351 = ADD
    { 350,	3,	1,	4,	1,	0,	0,	ColossusImpOpBase + 0,	195,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x2000000ULL },  // Inst #350 = ABS
    { 349,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	191,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = SUB_IMM
    { 348,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = STACKSAVE
    { 347,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = STACKRESTORE
    { 346,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	176,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = ST64_FI
    { 345,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	173,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = ST64_A_FI
    { 344,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	170,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = ST64_ACC_FI
    { 343,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = ST32_FI
    { 342,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	167,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = ST32_A_FI
    { 341,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	164,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = ST32_ACC_FI
    { 340,	1,	0,	0,	0,	0,	1,	ColossusImpOpBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = SETLR
    { 339,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	187,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = SELECT_V4F16
    { 338,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	187,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = SELECT_V2F32
    { 337,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	183,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = SELECT_V2F16
    { 336,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	183,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = SELECT_F32
    { 335,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	183,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = SELECT_F16
    { 334,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = RTN_REG_HOLDER
    { 333,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = RTN_PSEUDO
    { 332,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = MEM_BARRIER
    { 331,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = LDZ8_FI
    { 330,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = LDZ16_FI
    { 329,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	167,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = LDZ16_A_FI
    { 328,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = LDS8_FI
    { 327,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = LDS16_FI
    { 326,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = LDCONST_A
    { 325,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	179,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = LDCONST
    { 324,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	176,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = LD64_FI
    { 323,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	173,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = LD64_A_FI
    { 322,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	170,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = LD64_ACC_FI
    { 321,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = LD32_FI
    { 320,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	167,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = LD32_A_FI
    { 319,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	164,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = LD32_ACC_FI
    { 318,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = LABEL
    { 317,	2,	0,	0,	0,	1,	0,	ColossusImpOpBase + 2,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = ICALL
    { 316,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	163,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = FRAME_TO_ARGS_OFFSET
    { 315,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = FRAME_INDEX
    { 314,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = CLOOP_GUARD_BRANCH
    { 313,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = CLOOP_END_VALUE
    { 312,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = CLOOP_END_BRANCH
    { 311,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = CLOOP_BEGIN_VALUE
    { 310,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = CLOOP_BEGIN_TERMINATOR
    { 309,	1,	0,	0,	0,	0,	1,	ColossusImpOpBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = CALL_PSEUDO
    { 308,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = CALLIND
    { 307,	2,	0,	0,	0,	1,	1,	ColossusImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADJCALLSTACKUP
    { 306,	2,	0,	0,	0,	1,	1,	ColossusImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADJCALLSTACKDOWN
    { 305,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = G_UBFX
    { 304,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = G_SBFX
    { 303,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = G_VECREDUCE_UMIN
    { 302,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = G_VECREDUCE_UMAX
    { 301,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = G_VECREDUCE_SMIN
    { 300,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = G_VECREDUCE_SMAX
    { 299,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = G_VECREDUCE_XOR
    { 298,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = G_VECREDUCE_OR
    { 297,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = G_VECREDUCE_AND
    { 296,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = G_VECREDUCE_MUL
    { 295,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_VECREDUCE_ADD
    { 294,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_VECREDUCE_FMINIMUM
    { 293,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_FMAXIMUM
    { 292,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_FMIN
    { 291,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_FMAX
    { 290,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_FMUL
    { 289,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_FADD
    { 288,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_SEQ_FMUL
    { 287,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_SEQ_FADD
    { 286,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_UBSANTRAP
    { 285,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_DEBUGTRAP
    { 284,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_TRAP
    { 283,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_BZERO
    { 282,	4,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_MEMSET
    { 281,	4,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_MEMMOVE
    { 280,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_MEMCPY_INLINE
    { 279,	4,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_MEMCPY
    { 278,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #278 = G_WRITE_REGISTER
    { 277,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #277 = G_READ_REGISTER
    { 276,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_STRICT_FLDEXP
    { 275,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_STRICT_FSQRT
    { 274,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_STRICT_FMA
    { 273,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = G_STRICT_FREM
    { 272,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = G_STRICT_FDIV
    { 271,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_STRICT_FMUL
    { 270,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_STRICT_FSUB
    { 269,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_STRICT_FADD
    { 268,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_STACKRESTORE
    { 267,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_STACKSAVE
    { 266,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_DYN_STACKALLOC
    { 265,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_JUMP_TABLE
    { 264,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_BLOCK_ADDR
    { 263,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_ADDRSPACE_CAST
    { 262,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_FNEARBYINT
    { 261,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_FRINT
    { 260,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_FFLOOR
    { 259,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_FSQRT
    { 258,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_FTANH
    { 257,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_FSINH
    { 256,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_FCOSH
    { 255,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_FATAN2
    { 254,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_FATAN
    { 253,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_FASIN
    { 252,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FACOS
    { 251,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FTAN
    { 250,	3,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FSINCOS
    { 249,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FSIN
    { 248,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FCOS
    { 247,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FCEIL
    { 246,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_BITREVERSE
    { 245,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_BSWAP
    { 244,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_CTPOP
    { 243,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_CTLZ_ZERO_UNDEF
    { 242,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_CTLZ
    { 241,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_CTTZ_ZERO_UNDEF
    { 240,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_CTTZ
    { 239,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_VECTOR_COMPRESS
    { 238,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_STEP_VECTOR
    { 237,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_SPLAT_VECTOR
    { 236,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_SHUFFLE_VECTOR
    { 235,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_EXTRACT_VECTOR_ELT
    { 234,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_INSERT_VECTOR_ELT
    { 233,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_EXTRACT_SUBVECTOR
    { 232,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_INSERT_SUBVECTOR
    { 231,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_VSCALE
    { 230,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_BRJT
    { 229,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_BR
    { 228,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_LLROUND
    { 227,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_LROUND
    { 226,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_ABS
    { 225,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_UMAX
    { 224,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_UMIN
    { 223,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_SMAX
    { 222,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_SMIN
    { 221,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_PTRMASK
    { 220,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_PTR_ADD
    { 219,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_RESET_FPMODE
    { 218,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_SET_FPMODE
    { 217,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_GET_FPMODE
    { 216,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_RESET_FPENV
    { 215,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_SET_FPENV
    { 214,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_GET_FPENV
    { 213,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_FMAXIMUM
    { 212,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_FMINIMUM
    { 211,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_FMAXNUM_IEEE
    { 210,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_FMINNUM_IEEE
    { 209,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_FMAXNUM
    { 208,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_FMINNUM
    { 207,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_FCANONICALIZE
    { 206,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_IS_FPCLASS
    { 205,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FCOPYSIGN
    { 204,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_FABS
    { 203,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FPTOUI_SAT
    { 202,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FPTOSI_SAT
    { 201,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_UITOFP
    { 200,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_SITOFP
    { 199,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_FPTOUI
    { 198,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_FPTOSI
    { 197,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FPTRUNC
    { 196,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FPEXT
    { 195,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FNEG
    { 194,	3,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FFREXP
    { 193,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FLDEXP
    { 192,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FLOG10
    { 191,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FLOG2
    { 190,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FLOG
    { 189,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FEXP10
    { 188,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FEXP2
    { 187,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FEXP
    { 186,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FPOWI
    { 185,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FPOW
    { 184,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FREM
    { 183,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FDIV
    { 182,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FMAD
    { 181,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FMA
    { 180,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FMUL
    { 179,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FSUB
    { 178,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FADD
    { 177,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_UDIVFIXSAT
    { 176,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_SDIVFIXSAT
    { 175,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_UDIVFIX
    { 174,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_SDIVFIX
    { 173,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_UMULFIXSAT
    { 172,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_SMULFIXSAT
    { 171,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_UMULFIX
    { 170,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_SMULFIX
    { 169,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_SSHLSAT
    { 168,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_USHLSAT
    { 167,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SSUBSAT
    { 166,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_USUBSAT
    { 165,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SADDSAT
    { 164,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_UADDSAT
    { 163,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_SMULH
    { 162,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UMULH
    { 161,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SMULO
    { 160,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UMULO
    { 159,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SSUBE
    { 158,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_SSUBO
    { 157,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SADDE
    { 156,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SADDO
    { 155,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_USUBE
    { 154,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_USUBO
    { 153,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_UADDE
    { 152,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_UADDO
    { 151,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_SELECT
    { 150,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_UCMP
    { 149,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_SCMP
    { 148,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_FCMP
    { 147,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_ICMP
    { 146,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_ROTL
    { 145,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_ROTR
    { 144,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_FSHR
    { 143,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_FSHL
    { 142,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_ASHR
    { 141,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_LSHR
    { 140,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_SHL
    { 139,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_ZEXT
    { 138,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_SEXT_INREG
    { 137,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_SEXT
    { 136,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_VAARG
    { 135,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_VASTART
    { 134,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_FCONSTANT
    { 133,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_CONSTANT
    { 132,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_TRUNC
    { 131,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_ANYEXT
    { 130,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #130 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 129,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #129 = G_INTRINSIC_CONVERGENT
    { 128,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_INTRINSIC_W_SIDE_EFFECTS
    { 127,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_INTRINSIC
    { 126,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_INVOKE_REGION_START
    { 125,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_BRINDIRECT
    { 124,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_BRCOND
    { 123,	4,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_PREFETCH
    { 122,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_FENCE
    { 121,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_ATOMICRMW_USUB_SAT
    { 120,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_ATOMICRMW_USUB_COND
    { 119,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_ATOMICRMW_UDEC_WRAP
    { 118,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ATOMICRMW_UINC_WRAP
    { 117,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_ATOMICRMW_FMIN
    { 116,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_FMAX
    { 115,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_FSUB
    { 114,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FADD
    { 113,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_UMIN
    { 112,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_UMAX
    { 111,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_MIN
    { 110,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_MAX
    { 109,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_XOR
    { 108,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_OR
    { 107,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_NAND
    { 106,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_AND
    { 105,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_SUB
    { 104,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_ADD
    { 103,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_XCHG
    { 102,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMIC_CMPXCHG
    { 101,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 100,	5,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_INDEXED_STORE
    { 99,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_STORE
    { 98,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_INDEXED_ZEXTLOAD
    { 97,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_INDEXED_SEXTLOAD
    { 96,	5,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_INDEXED_LOAD
    { 95,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_ZEXTLOAD
    { 94,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_SEXTLOAD
    { 93,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_LOAD
    { 92,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_READSTEADYCOUNTER
    { 91,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_READCYCLECOUNTER
    { 90,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_INTRINSIC_ROUNDEVEN
    { 89,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_INTRINSIC_LLRINT
    { 88,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_INTRINSIC_LRINT
    { 87,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_ROUND
    { 86,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_TRUNC
    { 85,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
    { 84,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_CONSTANT_FOLD_BARRIER
    { 83,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_FREEZE
    { 82,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_BITCAST
    { 81,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_INTTOPTR
    { 80,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_PTRTOINT
    { 79,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_CONCAT_VECTORS
    { 78,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_BUILD_VECTOR_TRUNC
    { 77,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_BUILD_VECTOR
    { 76,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_MERGE_VALUES
    { 75,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_INSERT
    { 74,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_UNMERGE_VALUES
    { 73,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_EXTRACT
    { 72,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_CONSTANT_POOL
    { 71,	5,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
    { 70,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_GLOBAL_VALUE
    { 69,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_FRAME_INDEX
    { 68,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_PHI
    { 67,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_IMPLICIT_DEF
    { 66,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_ABDU
    { 65,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_ABDS
    { 64,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_XOR
    { 63,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_OR
    { 62,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_AND
    { 61,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_UDIVREM
    { 60,	4,	2,	0,	0,	0,	0,	ColossusImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_SDIVREM
    { 59,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_UREM
    { 58,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_SREM
    { 57,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_UDIV
    { 56,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_SDIV
    { 55,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_MUL
    { 54,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SUB
    { 53,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_ADD
    { 52,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ASSERT_ALIGN
    { 51,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ZEXT
    { 50,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_SEXT
    { 49,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #49 = CONVERGENCECTRL_GLUE
    { 48,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_LOOP
    { 47,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_ANCHOR
    { 46,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ENTRY
    { 45,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = JUMP_TABLE_DEBUG_INFO
    { 44,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = MEMBARRIER
    { 43,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = FAKE_USE
    { 42,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = ICALL_BRANCH_FUNNEL
    { 41,	3,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
    { 40,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_EVENT_CALL
    { 39,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_TAIL_CALL
    { 38,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_FUNCTION_EXIT
    { 37,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_RET
    { 36,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_FUNCTION_ENTER
    { 35,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_OP
    { 34,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = FAULTING_OP
    { 33,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = LOCAL_ESCAPE
    { 32,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = STATEPOINT
    { 31,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = PREALLOCATED_ARG
    { 30,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_SETUP
    { 29,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = LOAD_STACK_GUARD
    { 28,	6,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = PATCHPOINT
    { 27,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = FENTRY_CALL
    { 26,	2,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = STACKMAP
    { 25,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = ARITH_FENCE
    { 24,	4,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = PSEUDO_PROBE
    { 23,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = LIFETIME_END
    { 22,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_START
    { 21,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = BUNDLE
    { 20,	2,	1,	0,	5,	0,	0,	ColossusImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = COPY
    { 19,	2,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	ColossusImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	ColossusImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 154 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 157 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 160 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 163 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 164 */ { Colossus::ACCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 167 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 170 */ { Colossus::ACCPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 173 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 176 */ { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 179 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 181 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 183 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 187 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 191 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 195 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 198 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 202 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 206 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 210 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 214 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 217 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 221 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 224 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 226 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 229 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 231 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 235 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 239 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 242 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 245 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 250 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 255 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 260 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 263 */ { Colossus::ARQuadRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 265 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARQuadRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 268 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 272 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 277 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 281 */ { Colossus::ARQuadRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 286 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARQuadRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 292 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARQuadRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 298 */ { Colossus::ARQuadRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 303 */ { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 310 */ { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARQuadRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 317 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 322 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 328 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 334 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 340 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 346 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 351 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 356 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 361 */ { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 368 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 374 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 380 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 385 */ { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 390 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 397 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 404 */ { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 411 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 416 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 419 */ { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 422 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 428 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 434 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::ARRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 440 */ { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 446 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 452 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::ARPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 458 */ { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 462 */ { Colossus::MRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Colossus::MRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
  }, {
    /* 0 */
    /* 0 */ Colossus::SP, Colossus::SP,
    /* 2 */ Colossus::LR,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char ColossusInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "SWAP8_1\0"
  /* 26 */ "SORT8_1\0"
  /* 34 */ "SHUF8X8HI_1\0"
  /* 46 */ "SORT8X8HI_1\0"
  /* 58 */ "ROLL8L_1\0"
  /* 67 */ "SHUF8X8LO_1\0"
  /* 79 */ "SORT8X8LO_1\0"
  /* 91 */ "ROLL8R_1\0"
  /* 100 */ "LDD16V2A32\0"
  /* 111 */ "LD64A32\0"
  /* 119 */ "LDD16A32\0"
  /* 128 */ "LD32\0"
  /* 133 */ "URAND32\0"
  /* 141 */ "SELECT_V2F32\0"
  /* 154 */ "F16V2TOF32\0"
  /* 165 */ "F16TOF32\0"
  /* 174 */ "SELECT_F32\0"
  /* 185 */ "F32FROMI32\0"
  /* 196 */ "F32TOI32\0"
  /* 205 */ "F32FROMUI32\0"
  /* 217 */ "F32TOUI32\0"
  /* 227 */ "ROLL32\0"
  /* 234 */ "STM32\0"
  /* 240 */ "F32LOG2\0"
  /* 248 */ "F16V2LOG2\0"
  /* 258 */ "G_FLOG2\0"
  /* 266 */ "G_FATAN2\0"
  /* 275 */ "F32EXP2\0"
  /* 283 */ "F16V2EXP2\0"
  /* 293 */ "G_FEXP2\0"
  /* 301 */ "LDD16A64\0"
  /* 310 */ "ANDC64\0"
  /* 317 */ "URAND64\0"
  /* 325 */ "OR64\0"
  /* 330 */ "NOT64\0"
  /* 336 */ "LDB16B16\0"
  /* 345 */ "LDD16B16\0"
  /* 354 */ "LDB16\0"
  /* 360 */ "SELECT_V2F16\0"
  /* 373 */ "SELECT_V4F16\0"
  /* 386 */ "F32TOF16\0"
  /* 395 */ "F32V2TOF16\0"
  /* 406 */ "F8V2TOF16\0"
  /* 416 */ "F32V4TOF16\0"
  /* 427 */ "F8V4TOF16\0"
  /* 437 */ "SELECT_F16\0"
  /* 448 */ "ROLL16\0"
  /* 455 */ "LDS16\0"
  /* 461 */ "LDZ16\0"
  /* 467 */ "LD128\0"
  /* 473 */ "LDB8\0"
  /* 478 */ "F16V2TOF8\0"
  /* 488 */ "F16V8TOF8\0"
  /* 498 */ "SWAP8\0"
  /* 504 */ "LDS8\0"
  /* 509 */ "SORT8\0"
  /* 515 */ "BITREV8\0"
  /* 523 */ "LDZ8\0"
  /* 528 */ "G_FMA\0"
  /* 534 */ "G_STRICT_FMA\0"
  /* 547 */ "F32V2GINA\0"
  /* 557 */ "F16V2GINA\0"
  /* 567 */ "LD32_A\0"
  /* 574 */ "ST32_A\0"
  /* 581 */ "LD64_A\0"
  /* 588 */ "ST64_A\0"
  /* 595 */ "ROLL16_A\0"
  /* 604 */ "ANDC_A\0"
  /* 611 */ "AND_A\0"
  /* 617 */ "SORT4X16HI_A\0"
  /* 630 */ "LD32STEP_SI_A\0"
  /* 644 */ "ST32STEP_SI_A\0"
  /* 658 */ "LD64STEP_SI_A\0"
  /* 672 */ "ST64STEP_SI_A\0"
  /* 686 */ "SETZI_A\0"
  /* 694 */ "LD32_ZI_A\0"
  /* 704 */ "ST32_ZI_A\0"
  /* 714 */ "LD64_ZI_A\0"
  /* 724 */ "ST64_ZI_A\0"
  /* 734 */ "ANDC_ZI_A\0"
  /* 744 */ "AND_ZI_A\0"
  /* 753 */ "OR_ZI_A\0"
  /* 761 */ "SORT4X16LO_A\0"
  /* 774 */ "LD32STEP_A\0"
  /* 785 */ "ST32STEP_A\0"
  /* 796 */ "LD64STEP_A\0"
  /* 807 */ "ST64STEP_A\0"
  /* 818 */ "OR_A\0"
  /* 823 */ "LDCONST_A\0"
  /* 833 */ "ANDC_IZ_A\0"
  /* 843 */ "AND_IZ_A\0"
  /* 852 */ "OR_IZ_A\0"
  /* 860 */ "F32SUB\0"
  /* 867 */ "F32V2SUB\0"
  /* 876 */ "F16V2SUB\0"
  /* 885 */ "F16V4SUB\0"
  /* 894 */ "G_FSUB\0"
  /* 901 */ "G_STRICT_FSUB\0"
  /* 915 */ "G_ATOMICRMW_FSUB\0"
  /* 932 */ "G_SUB\0"
  /* 938 */ "G_ATOMICRMW_SUB\0"
  /* 954 */ "F32MAC\0"
  /* 961 */ "F32V2MAC\0"
  /* 970 */ "F16V2CMAC\0"
  /* 980 */ "F16V4CMAC\0"
  /* 990 */ "F32V4ACC\0"
  /* 999 */ "F16V4ACC\0"
  /* 1008 */ "F16V8ACC\0"
  /* 1017 */ "F16V4GACC\0"
  /* 1027 */ "F32V4SQACC\0"
  /* 1038 */ "F16V8SQACC\0"
  /* 1049 */ "F32V4ABSACC\0"
  /* 1061 */ "F16V4ABSACC\0"
  /* 1073 */ "F16V8ABSACC\0"
  /* 1085 */ "F16V4STACC\0"
  /* 1096 */ "F16V4ISTACC\0"
  /* 1108 */ "ANDC\0"
  /* 1113 */ "BRNZDEC\0"
  /* 1121 */ "F16V4HIHOV4SLIC\0"
  /* 1137 */ "F8V8HIHOV4SLIC\0"
  /* 1152 */ "F16V4HIHOSLIC\0"
  /* 1166 */ "F16V4SIHOSLIC\0"
  /* 1180 */ "F32SISOSLIC\0"
  /* 1192 */ "F16V4SISOSLIC\0"
  /* 1206 */ "G_INTRINSIC\0"
  /* 1218 */ "G_FPTRUNC\0"
  /* 1228 */ "G_INTRINSIC_TRUNC\0"
  /* 1246 */ "G_TRUNC\0"
  /* 1254 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 1275 */ "G_DYN_STACKALLOC\0"
  /* 1292 */ "POPC\0"
  /* 1297 */ "F16V2MAXC\0"
  /* 1307 */ "F16V4MAXC\0"
  /* 1317 */ "G_FMAD\0"
  /* 1324 */ "G_INDEXED_SEXTLOAD\0"
  /* 1343 */ "G_SEXTLOAD\0"
  /* 1354 */ "G_INDEXED_ZEXTLOAD\0"
  /* 1373 */ "G_ZEXTLOAD\0"
  /* 1384 */ "G_INDEXED_LOAD\0"
  /* 1399 */ "G_LOAD\0"
  /* 1406 */ "F32ADD\0"
  /* 1413 */ "F32V2ADD\0"
  /* 1422 */ "F16V2ADD\0"
  /* 1431 */ "F16V4ADD\0"
  /* 1440 */ "G_VECREDUCE_FADD\0"
  /* 1457 */ "G_FADD\0"
  /* 1464 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 1485 */ "G_STRICT_FADD\0"
  /* 1499 */ "G_ATOMICRMW_FADD\0"
  /* 1516 */ "F32ABSADD\0"
  /* 1526 */ "F32V2ABSADD\0"
  /* 1538 */ "F16V2ABSADD\0"
  /* 1550 */ "F16V4ABSADD\0"
  /* 1562 */ "G_VECREDUCE_ADD\0"
  /* 1578 */ "G_ADD\0"
  /* 1584 */ "G_PTR_ADD\0"
  /* 1594 */ "G_ATOMICRMW_ADD\0"
  /* 1610 */ "F32SIGMOID\0"
  /* 1621 */ "F16V2SIGMOID\0"
  /* 1634 */ "G_ATOMICRMW_NAND\0"
  /* 1651 */ "F32V2GRAND\0"
  /* 1662 */ "F16V2GRAND\0"
  /* 1673 */ "G_VECREDUCE_AND\0"
  /* 1689 */ "G_AND\0"
  /* 1695 */ "G_ATOMICRMW_AND\0"
  /* 1711 */ "LIFETIME_END\0"
  /* 1724 */ "CALLIND\0"
  /* 1732 */ "BRIND\0"
  /* 1738 */ "G_BRCOND\0"
  /* 1747 */ "G_ATOMICRMW_USUB_COND\0"
  /* 1769 */ "G_LLROUND\0"
  /* 1779 */ "G_LROUND\0"
  /* 1788 */ "G_INTRINSIC_ROUND\0"
  /* 1806 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 1832 */ "LOAD_STACK_GUARD\0"
  /* 1849 */ "PSEUDO_PROBE\0"
  /* 1862 */ "G_SSUBE\0"
  /* 1870 */ "G_USUBE\0"
  /* 1878 */ "LD64A32PACE\0"
  /* 1890 */ "LDST64PACE\0"
  /* 1901 */ "LD2XST64PACE\0"
  /* 1914 */ "LD2X64PACE\0"
  /* 1925 */ "LD64B16PACE\0"
  /* 1937 */ "G_FENCE\0"
  /* 1945 */ "ARITH_FENCE\0"
  /* 1957 */ "REG_SEQUENCE\0"
  /* 1970 */ "G_SADDE\0"
  /* 1978 */ "G_UADDE\0"
  /* 1986 */ "G_GET_FPMODE\0"
  /* 1999 */ "G_RESET_FPMODE\0"
  /* 2014 */ "G_SET_FPMODE\0"
  /* 2027 */ "G_FMINNUM_IEEE\0"
  /* 2042 */ "G_FMAXNUM_IEEE\0"
  /* 2057 */ "F32CMPGE\0"
  /* 2066 */ "F32V2CMPGE\0"
  /* 2077 */ "F16V2CMPGE\0"
  /* 2088 */ "F16V4CMPGE\0"
  /* 2099 */ "G_VSCALE\0"
  /* 2108 */ "G_JUMP_TABLE\0"
  /* 2121 */ "BUNDLE\0"
  /* 2128 */ "F32CMPLE\0"
  /* 2137 */ "F32V2CMPLE\0"
  /* 2148 */ "F16V2CMPLE\0"
  /* 2159 */ "F16V4CMPLE\0"
  /* 2170 */ "G_MEMCPY_INLINE\0"
  /* 2186 */ "F32CMPNE\0"
  /* 2195 */ "F32V2CMPNE\0"
  /* 2206 */ "F16V2CMPNE\0"
  /* 2217 */ "F16V4CMPNE\0"
  /* 2228 */ "LOCAL_ESCAPE\0"
  /* 2241 */ "G_STACKRESTORE\0"
  /* 2256 */ "G_INDEXED_STORE\0"
  /* 2272 */ "G_STORE\0"
  /* 2280 */ "G_BITREVERSE\0"
  /* 2293 */ "FAKE_USE\0"
  /* 2302 */ "CLOOP_END_VALUE\0"
  /* 2318 */ "DBG_VALUE\0"
  /* 2328 */ "G_GLOBAL_VALUE\0"
  /* 2343 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 2366 */ "CLOOP_BEGIN_VALUE\0"
  /* 2384 */ "CONVERGENCECTRL_GLUE\0"
  /* 2405 */ "G_STACKSAVE\0"
  /* 2417 */ "G_MEMMOVE\0"
  /* 2427 */ "G_FREEZE\0"
  /* 2436 */ "G_FCANONICALIZE\0"
  /* 2452 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 2470 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 2488 */ "INIT_UNDEF\0"
  /* 2499 */ "G_IMPLICIT_DEF\0"
  /* 2514 */ "DBG_INSTR_REF\0"
  /* 2528 */ "G_FNEG\0"
  /* 2535 */ "BRNEG\0"
  /* 2541 */ "EXITNEG\0"
  /* 2549 */ "EXTRACT_SUBREG\0"
  /* 2564 */ "INSERT_SUBREG\0"
  /* 2578 */ "G_SEXT_INREG\0"
  /* 2591 */ "SUBREG_TO_REG\0"
  /* 2605 */ "G_ATOMIC_CMPXCHG\0"
  /* 2622 */ "G_ATOMICRMW_XCHG\0"
  /* 2639 */ "G_FLOG\0"
  /* 2646 */ "G_VAARG\0"
  /* 2654 */ "PREALLOCATED_ARG\0"
  /* 2671 */ "CLOOP_END_BRANCH\0"
  /* 2688 */ "CLOOP_GUARD_BRANCH\0"
  /* 2707 */ "G_PREFETCH\0"
  /* 2718 */ "G_SMULH\0"
  /* 2726 */ "G_UMULH\0"
  /* 2734 */ "F32TANH\0"
  /* 2742 */ "F16V2TANH\0"
  /* 2752 */ "G_FTANH\0"
  /* 2760 */ "G_FSINH\0"
  /* 2768 */ "G_FCOSH\0"
  /* 2776 */ "LD32_FI\0"
  /* 2784 */ "ST32_FI\0"
  /* 2792 */ "LD64_FI\0"
  /* 2800 */ "ST64_FI\0"
  /* 2808 */ "LDS16_FI\0"
  /* 2817 */ "LDZ16_FI\0"
  /* 2826 */ "LDS8_FI\0"
  /* 2834 */ "LDZ8_FI\0"
  /* 2842 */ "LD32_A_FI\0"
  /* 2852 */ "ST32_A_FI\0"
  /* 2862 */ "LD64_A_FI\0"
  /* 2872 */ "ST64_A_FI\0"
  /* 2882 */ "LDZ16_A_FI\0"
  /* 2893 */ "LD32_ACC_FI\0"
  /* 2905 */ "ST32_ACC_FI\0"
  /* 2917 */ "LD64_ACC_FI\0"
  /* 2929 */ "ST64_ACC_FI\0"
  /* 2941 */ "SORT4X32HI\0"
  /* 2952 */ "SORT4X16HI\0"
  /* 2963 */ "SHUF8X8HI\0"
  /* 2973 */ "SORT8X8HI\0"
  /* 2983 */ "DBG_PHI\0"
  /* 2991 */ "G_FPTOSI\0"
  /* 3000 */ "SUB_SI\0"
  /* 3007 */ "ADD_SI\0"
  /* 3014 */ "MUL_SI\0"
  /* 3021 */ "MIN_SI\0"
  /* 3028 */ "LD32STEP_SI\0"
  /* 3040 */ "ST32STEP_SI\0"
  /* 3052 */ "LDB16STEP_SI\0"
  /* 3065 */ "LDS16STEP_SI\0"
  /* 3078 */ "LDZ16STEP_SI\0"
  /* 3091 */ "LD128STEP_SI\0"
  /* 3104 */ "LDS8STEP_SI\0"
  /* 3116 */ "LDZ8STEP_SI\0"
  /* 3128 */ "CMPEQ_SI\0"
  /* 3137 */ "CMPSLT_SI\0"
  /* 3147 */ "MAX_SI\0"
  /* 3154 */ "F32SUFROMUI\0"
  /* 3166 */ "F32V2SUFROMUI\0"
  /* 3180 */ "F16V2SUFROMUI\0"
  /* 3194 */ "F16V4SUFROMUI\0"
  /* 3208 */ "G_FPTOUI\0"
  /* 3217 */ "G_FPOWI\0"
  /* 3225 */ "SETZI\0"
  /* 3231 */ "LD32_ZI\0"
  /* 3239 */ "ST32_ZI\0"
  /* 3247 */ "LDB16_ZI\0"
  /* 3256 */ "LDS16_ZI\0"
  /* 3265 */ "LDZ16_ZI\0"
  /* 3274 */ "LD128_ZI\0"
  /* 3283 */ "LDB8_ZI\0"
  /* 3291 */ "LDS8_ZI\0"
  /* 3299 */ "LDZ8_ZI\0"
  /* 3307 */ "SUB_ZI\0"
  /* 3314 */ "ANDC_ZI\0"
  /* 3322 */ "ADD_ZI\0"
  /* 3329 */ "AND_ZI\0"
  /* 3336 */ "SHL_ZI\0"
  /* 3343 */ "MIN_ZI\0"
  /* 3350 */ "CMPEQ_ZI\0"
  /* 3359 */ "SHR_ZI\0"
  /* 3366 */ "OR_ZI\0"
  /* 3372 */ "SHRS_ZI\0"
  /* 3380 */ "CMPULT_ZI\0"
  /* 3390 */ "RPT_ZI\0"
  /* 3397 */ "MAX_ZI\0"
  /* 3404 */ "TAPACK\0"
  /* 3411 */ "F32V2RMASK\0"
  /* 3422 */ "F16V4RMASK\0"
  /* 3433 */ "G_PTRMASK\0"
  /* 3443 */ "ROLL8L\0"
  /* 3450 */ "F32V2SUB_BL\0"
  /* 3462 */ "F16V2SUB_BL\0"
  /* 3474 */ "F16V4SUB_BL\0"
  /* 3486 */ "F32V2ADD_BL\0"
  /* 3498 */ "F16V2ADD_BL\0"
  /* 3510 */ "F16V4ADD_BL\0"
  /* 3522 */ "F32V2CMPGE_BL\0"
  /* 3536 */ "F16V2CMPGE_BL\0"
  /* 3550 */ "F16V4CMPGE_BL\0"
  /* 3564 */ "F32V2CMPLE_BL\0"
  /* 3578 */ "F16V2CMPLE_BL\0"
  /* 3592 */ "F16V4CMPLE_BL\0"
  /* 3606 */ "F32V2CMPNE_BL\0"
  /* 3620 */ "F16V2CMPNE_BL\0"
  /* 3634 */ "F16V4CMPNE_BL\0"
  /* 3648 */ "F32V2MUL_BL\0"
  /* 3660 */ "F16V2MUL_BL\0"
  /* 3672 */ "F16V4MUL_BL\0"
  /* 3684 */ "F32V2CMPEQ_BL\0"
  /* 3698 */ "F16V2CMPEQ_BL\0"
  /* 3712 */ "F16V4CMPEQ_BL\0"
  /* 3726 */ "F32V2CMPGT_BL\0"
  /* 3740 */ "F16V2CMPGT_BL\0"
  /* 3754 */ "F16V4CMPGT_BL\0"
  /* 3768 */ "F32V2CMPLT_BL\0"
  /* 3782 */ "F16V2CMPLT_BL\0"
  /* 3796 */ "F16V4CMPLT_BL\0"
  /* 3810 */ "GC_LABEL\0"
  /* 3819 */ "DBG_LABEL\0"
  /* 3829 */ "EH_LABEL\0"
  /* 3838 */ "ANNOTATION_LABEL\0"
  /* 3855 */ "ICALL_BRANCH_FUNNEL\0"
  /* 3875 */ "G_FSHL\0"
  /* 3882 */ "G_SHL\0"
  /* 3888 */ "G_FCEIL\0"
  /* 3896 */ "ICALL\0"
  /* 3902 */ "PATCHABLE_TAIL_CALL\0"
  /* 3922 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 3949 */ "PATCHABLE_EVENT_CALL\0"
  /* 3970 */ "FENTRY_CALL\0"
  /* 3982 */ "RUNALL\0"
  /* 3989 */ "KILL\0"
  /* 3994 */ "G_CONSTANT_POOL\0"
  /* 4010 */ "G_ROTL\0"
  /* 4017 */ "F32MUL\0"
  /* 4024 */ "F32V2MUL\0"
  /* 4033 */ "F16V2MUL\0"
  /* 4042 */ "F16V4MUL\0"
  /* 4051 */ "G_VECREDUCE_FMUL\0"
  /* 4068 */ "G_FMUL\0"
  /* 4075 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 4096 */ "G_STRICT_FMUL\0"
  /* 4110 */ "G_VECREDUCE_MUL\0"
  /* 4126 */ "G_MUL\0"
  /* 4132 */ "G_FREM\0"
  /* 4139 */ "G_STRICT_FREM\0"
  /* 4153 */ "G_SREM\0"
  /* 4160 */ "G_UREM\0"
  /* 4167 */ "G_SDIVREM\0"
  /* 4177 */ "G_UDIVREM\0"
  /* 4187 */ "SUB_IMM\0"
  /* 4195 */ "ATOM\0"
  /* 4200 */ "INLINEASM\0"
  /* 4210 */ "G_VECREDUCE_FMINIMUM\0"
  /* 4231 */ "G_FMINIMUM\0"
  /* 4242 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 4263 */ "G_FMAXIMUM\0"
  /* 4274 */ "G_FMINNUM\0"
  /* 4284 */ "G_FMAXNUM\0"
  /* 4294 */ "F16V2SUM\0"
  /* 4303 */ "F16V4SUM\0"
  /* 4312 */ "G_FATAN\0"
  /* 4320 */ "G_FTAN\0"
  /* 4327 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 4349 */ "G_ASSERT_ALIGN\0"
  /* 4364 */ "G_FCOPYSIGN\0"
  /* 4376 */ "F32MIN\0"
  /* 4383 */ "F32V2MIN\0"
  /* 4392 */ "F16V2MIN\0"
  /* 4401 */ "F16V4MIN\0"
  /* 4410 */ "G_VECREDUCE_FMIN\0"
  /* 4427 */ "G_ATOMICRMW_FMIN\0"
  /* 4444 */ "G_VECREDUCE_SMIN\0"
  /* 4461 */ "G_SMIN\0"
  /* 4468 */ "G_VECREDUCE_UMIN\0"
  /* 4485 */ "G_UMIN\0"
  /* 4492 */ "G_ATOMICRMW_UMIN\0"
  /* 4509 */ "G_ATOMICRMW_MIN\0"
  /* 4525 */ "G_FASIN\0"
  /* 4533 */ "G_FSIN\0"
  /* 4540 */ "F32LN\0"
  /* 4546 */ "F16V2LN\0"
  /* 4554 */ "CFI_INSTRUCTION\0"
  /* 4570 */ "RTN\0"
  /* 4574 */ "RUN\0"
  /* 4578 */ "ADJCALLSTACKDOWN\0"
  /* 4595 */ "G_SSUBO\0"
  /* 4603 */ "G_USUBO\0"
  /* 4611 */ "G_SADDO\0"
  /* 4619 */ "G_UADDO\0"
  /* 4627 */ "CALL_PSEUDO\0"
  /* 4639 */ "RTN_PSEUDO\0"
  /* 4650 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 4672 */ "SORT4X32LO\0"
  /* 4683 */ "SORT4X16LO\0"
  /* 4694 */ "SHUF8X8LO\0"
  /* 4704 */ "SORT8X8LO\0"
  /* 4714 */ "G_SMULO\0"
  /* 4722 */ "G_UMULO\0"
  /* 4730 */ "G_BZERO\0"
  /* 4738 */ "STACKMAP\0"
  /* 4747 */ "G_DEBUGTRAP\0"
  /* 4759 */ "G_UBSANTRAP\0"
  /* 4771 */ "G_TRAP\0"
  /* 4778 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 4800 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 4822 */ "G_BSWAP\0"
  /* 4830 */ "LD32STEP\0"
  /* 4839 */ "STM32STEP\0"
  /* 4849 */ "LDB16STEP\0"
  /* 4859 */ "LDS16STEP\0"
  /* 4869 */ "LDZ16STEP\0"
  /* 4879 */ "LD128STEP\0"
  /* 4889 */ "LDS8STEP\0"
  /* 4898 */ "LDZ8STEP\0"
  /* 4907 */ "G_SITOFP\0"
  /* 4916 */ "G_UITOFP\0"
  /* 4925 */ "F32SISOV2AMP\0"
  /* 4938 */ "F16V4HIHOV4AMP\0"
  /* 4953 */ "F8V8HIHOV4AMP\0"
  /* 4967 */ "F32CLAMP\0"
  /* 4976 */ "F32V2CLAMP\0"
  /* 4987 */ "F16V2CLAMP\0"
  /* 4998 */ "F16V4CLAMP\0"
  /* 5009 */ "F16V4HIHOAMP\0"
  /* 5022 */ "F16V4SIHOAMP\0"
  /* 5035 */ "F32SISOAMP\0"
  /* 5046 */ "F16V4SISOAMP\0"
  /* 5059 */ "G_FCMP\0"
  /* 5066 */ "G_ICMP\0"
  /* 5073 */ "G_SCMP\0"
  /* 5080 */ "G_UCMP\0"
  /* 5087 */ "F32V2AOP\0"
  /* 5096 */ "CONVERGENCECTRL_LOOP\0"
  /* 5117 */ "G_CTPOP\0"
  /* 5125 */ "PATCHABLE_OP\0"
  /* 5138 */ "FAULTING_OP\0"
  /* 5150 */ "ADJCALLSTACKUP\0"
  /* 5165 */ "PREALLOCATED_SETUP\0"
  /* 5184 */ "F32EXP\0"
  /* 5191 */ "F16V2EXP\0"
  /* 5200 */ "G_FLDEXP\0"
  /* 5209 */ "G_STRICT_FLDEXP\0"
  /* 5225 */ "G_FEXP\0"
  /* 5232 */ "G_FFREXP\0"
  /* 5241 */ "F32CMPEQ\0"
  /* 5250 */ "F32V2CMPEQ\0"
  /* 5261 */ "F16V2CMPEQ\0"
  /* 5272 */ "F16V4CMPEQ\0"
  /* 5283 */ "ROLL8R\0"
  /* 5290 */ "G_BR\0"
  /* 5295 */ "INLINEASM_BR\0"
  /* 5308 */ "G_BLOCK_ADDR\0"
  /* 5321 */ "RTN_REG_HOLDER\0"
  /* 5336 */ "MEMBARRIER\0"
  /* 5347 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 5371 */ "MEM_BARRIER\0"
  /* 5383 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 5408 */ "G_READCYCLECOUNTER\0"
  /* 5427 */ "G_READSTEADYCOUNTER\0"
  /* 5447 */ "G_READ_REGISTER\0"
  /* 5463 */ "G_WRITE_REGISTER\0"
  /* 5480 */ "G_ASHR\0"
  /* 5487 */ "G_FSHR\0"
  /* 5494 */ "G_LSHR\0"
  /* 5501 */ "SETLR\0"
  /* 5507 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 5530 */ "XNOR\0"
  /* 5535 */ "G_FFLOOR\0"
  /* 5544 */ "CLOOP_BEGIN_TERMINATOR\0"
  /* 5567 */ "G_EXTRACT_SUBVECTOR\0"
  /* 5587 */ "G_INSERT_SUBVECTOR\0"
  /* 5606 */ "G_BUILD_VECTOR\0"
  /* 5621 */ "G_SHUFFLE_VECTOR\0"
  /* 5638 */ "G_STEP_VECTOR\0"
  /* 5652 */ "G_SPLAT_VECTOR\0"
  /* 5667 */ "G_VECREDUCE_XOR\0"
  /* 5683 */ "G_XOR\0"
  /* 5689 */ "G_ATOMICRMW_XOR\0"
  /* 5705 */ "G_VECREDUCE_OR\0"
  /* 5720 */ "G_OR\0"
  /* 5725 */ "G_ATOMICRMW_OR\0"
  /* 5740 */ "G_ROTR\0"
  /* 5747 */ "G_INTTOPTR\0"
  /* 5758 */ "G_FABS\0"
  /* 5765 */ "G_ABS\0"
  /* 5771 */ "LD64PUTCS\0"
  /* 5781 */ "LD128PUTCS\0"
  /* 5792 */ "G_ABDS\0"
  /* 5799 */ "G_UNMERGE_VALUES\0"
  /* 5816 */ "G_MERGE_VALUES\0"
  /* 5831 */ "CMS\0"
  /* 5835 */ "G_FACOS\0"
  /* 5843 */ "G_FCOS\0"
  /* 5850 */ "G_FSINCOS\0"
  /* 5860 */ "BRPOS\0"
  /* 5866 */ "EXITPOS\0"
  /* 5874 */ "SHRS\0"
  /* 5879 */ "G_CONCAT_VECTORS\0"
  /* 5896 */ "F32CLASS\0"
  /* 5905 */ "F32V2CLASS\0"
  /* 5916 */ "F16V2CLASS\0"
  /* 5927 */ "F16V4CLASS\0"
  /* 5938 */ "F8V4CLASS\0"
  /* 5948 */ "COPY_TO_REGCLASS\0"
  /* 5965 */ "G_IS_FPCLASS\0"
  /* 5978 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 6008 */ "G_VECTOR_COMPRESS\0"
  /* 6026 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 6053 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 6091 */ "G_SSUBSAT\0"
  /* 6101 */ "G_USUBSAT\0"
  /* 6111 */ "G_SADDSAT\0"
  /* 6121 */ "G_UADDSAT\0"
  /* 6131 */ "G_SSHLSAT\0"
  /* 6141 */ "G_USHLSAT\0"
  /* 6151 */ "G_SMULFIXSAT\0"
  /* 6164 */ "G_UMULFIXSAT\0"
  /* 6177 */ "G_SDIVFIXSAT\0"
  /* 6190 */ "G_UDIVFIXSAT\0"
  /* 6203 */ "G_ATOMICRMW_USUB_SAT\0"
  /* 6224 */ "G_FPTOSI_SAT\0"
  /* 6237 */ "G_FPTOUI_SAT\0"
  /* 6250 */ "G_EXTRACT\0"
  /* 6260 */ "G_SELECT\0"
  /* 6269 */ "G_BRINDIRECT\0"
  /* 6282 */ "UGET\0"
  /* 6287 */ "PATCHABLE_RET\0"
  /* 6301 */ "FRAME_TO_ARGS_OFFSET\0"
  /* 6322 */ "G_MEMSET\0"
  /* 6331 */ "F32CMPGT\0"
  /* 6340 */ "F32V2CMPGT\0"
  /* 6351 */ "F16V2CMPGT\0"
  /* 6362 */ "F16V4CMPGT\0"
  /* 6373 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 6397 */ "G_BRJT\0"
  /* 6404 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 6425 */ "G_INSERT_VECTOR_ELT\0"
  /* 6445 */ "F32CMPLT\0"
  /* 6454 */ "F32V2CMPLT\0"
  /* 6465 */ "F16V2CMPLT\0"
  /* 6476 */ "F16V4CMPLT\0"
  /* 6487 */ "CMPSLT\0"
  /* 6494 */ "CMPULT\0"
  /* 6501 */ "G_FCONSTANT\0"
  /* 6513 */ "G_CONSTANT\0"
  /* 6524 */ "G_INTRINSIC_CONVERGENT\0"
  /* 6547 */ "F32INT\0"
  /* 6554 */ "STATEPOINT\0"
  /* 6565 */ "PATCHPOINT\0"
  /* 6576 */ "G_PTRTOINT\0"
  /* 6587 */ "G_FRINT\0"
  /* 6595 */ "G_INTRINSIC_LLRINT\0"
  /* 6614 */ "G_INTRINSIC_LRINT\0"
  /* 6632 */ "G_FNEARBYINT\0"
  /* 6645 */ "NOT\0"
  /* 6649 */ "RPT\0"
  /* 6653 */ "G_VASTART\0"
  /* 6663 */ "LIFETIME_START\0"
  /* 6678 */ "G_INVOKE_REGION_START\0"
  /* 6700 */ "G_INSERT\0"
  /* 6709 */ "F32SQRT\0"
  /* 6717 */ "G_FSQRT\0"
  /* 6725 */ "G_STRICT_FSQRT\0"
  /* 6740 */ "G_BITCAST\0"
  /* 6750 */ "G_ADDRSPACE_CAST\0"
  /* 6767 */ "DBG_VALUE_LIST\0"
  /* 6782 */ "LDCONST\0"
  /* 6790 */ "UPUT\0"
  /* 6795 */ "G_FPEXT\0"
  /* 6803 */ "G_SEXT\0"
  /* 6810 */ "G_ASSERT_SEXT\0"
  /* 6824 */ "G_ANYEXT\0"
  /* 6833 */ "G_ZEXT\0"
  /* 6840 */ "G_ASSERT_ZEXT\0"
  /* 6854 */ "F16V2SUB_BU\0"
  /* 6866 */ "F16V4SUB_BU\0"
  /* 6878 */ "F16V2ADD_BU\0"
  /* 6890 */ "F16V4ADD_BU\0"
  /* 6902 */ "F16V2CMPGE_BU\0"
  /* 6916 */ "F16V4CMPGE_BU\0"
  /* 6930 */ "F16V2CMPLE_BU\0"
  /* 6944 */ "F16V4CMPLE_BU\0"
  /* 6958 */ "F16V2CMPNE_BU\0"
  /* 6972 */ "F16V4CMPNE_BU\0"
  /* 6986 */ "F16V2MUL_BU\0"
  /* 6998 */ "F16V4MUL_BU\0"
  /* 7010 */ "SORT4X16LO_BU\0"
  /* 7024 */ "F16V2CMPEQ_BU\0"
  /* 7038 */ "F16V4CMPEQ_BU\0"
  /* 7052 */ "F16V2CMPGT_BU\0"
  /* 7066 */ "F16V4CMPGT_BU\0"
  /* 7080 */ "F16V2CMPLT_BU\0"
  /* 7094 */ "F16V4CMPLT_BU\0"
  /* 7108 */ "G_ABDU\0"
  /* 7115 */ "F32DIV\0"
  /* 7122 */ "G_FDIV\0"
  /* 7129 */ "G_STRICT_FDIV\0"
  /* 7143 */ "G_SDIV\0"
  /* 7150 */ "G_UDIV\0"
  /* 7157 */ "G_GET_FPENV\0"
  /* 7169 */ "G_RESET_FPENV\0"
  /* 7183 */ "G_SET_FPENV\0"
  /* 7195 */ "G_FPOW\0"
  /* 7202 */ "F32MAX\0"
  /* 7209 */ "F32V2MAX\0"
  /* 7218 */ "F16V2MAX\0"
  /* 7227 */ "F16V4MAX\0"
  /* 7236 */ "G_VECREDUCE_FMAX\0"
  /* 7253 */ "G_ATOMICRMW_FMAX\0"
  /* 7270 */ "F32ABSMAX\0"
  /* 7280 */ "F32V2ABSMAX\0"
  /* 7292 */ "F16V2ABSMAX\0"
  /* 7304 */ "F16V4ABSMAX\0"
  /* 7316 */ "G_VECREDUCE_SMAX\0"
  /* 7333 */ "G_SMAX\0"
  /* 7340 */ "G_VECREDUCE_UMAX\0"
  /* 7357 */ "G_UMAX\0"
  /* 7364 */ "G_ATOMICRMW_UMAX\0"
  /* 7381 */ "G_ATOMICRMW_MAX\0"
  /* 7397 */ "G_FRAME_INDEX\0"
  /* 7411 */ "G_SBFX\0"
  /* 7418 */ "G_UBFX\0"
  /* 7425 */ "G_SMULFIX\0"
  /* 7435 */ "G_UMULFIX\0"
  /* 7445 */ "G_SDIVFIX\0"
  /* 7455 */ "G_UDIVFIX\0"
  /* 7465 */ "F16V4MIX\0"
  /* 7474 */ "F32OOX\0"
  /* 7481 */ "F32OORX\0"
  /* 7489 */ "G_MEMCPY\0"
  /* 7498 */ "COPY\0"
  /* 7503 */ "F32V2AXPY\0"
  /* 7513 */ "CONVERGENCECTRL_ENTRY\0"
  /* 7535 */ "OR_IZ\0"
  /* 7541 */ "CLZ\0"
  /* 7545 */ "G_CTLZ\0"
  /* 7552 */ "BRNZ\0"
  /* 7557 */ "EXITNZ\0"
  /* 7564 */ "BRZ\0"
  /* 7568 */ "EXITZ\0"
  /* 7574 */ "G_CTTZ\0"
  /* 7581 */ "MOVZ\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned ColossusInstrNameIndices[] = {
    2987U, 4200U, 5295U, 4554U, 3829U, 3810U, 3838U, 3989U, 
    2549U, 2564U, 2501U, 2488U, 2591U, 5948U, 2318U, 6767U, 
    2514U, 2983U, 3819U, 1957U, 7498U, 2121U, 6663U, 1711U, 
    1849U, 1945U, 4738U, 3970U, 6565U, 1832U, 5165U, 2654U, 
    6554U, 2228U, 5138U, 5125U, 5383U, 6287U, 6373U, 3902U, 
    3949U, 3922U, 3855U, 2293U, 5336U, 4650U, 7513U, 5507U, 
    5096U, 2384U, 6810U, 6840U, 4349U, 1578U, 932U, 4126U, 
    7143U, 7150U, 4153U, 4160U, 4167U, 4177U, 1689U, 5720U, 
    5683U, 5792U, 7108U, 2499U, 2985U, 7397U, 2328U, 2343U, 
    3994U, 6250U, 5799U, 6700U, 5816U, 5606U, 1254U, 5879U, 
    6576U, 5747U, 6740U, 2427U, 5347U, 1806U, 1228U, 1788U, 
    6614U, 6595U, 4327U, 5408U, 5427U, 1399U, 1343U, 1373U, 
    1384U, 1324U, 1354U, 2272U, 2256U, 5978U, 2605U, 2622U, 
    1594U, 938U, 1695U, 1634U, 5725U, 5689U, 7381U, 4509U, 
    7364U, 4492U, 1499U, 915U, 7253U, 4427U, 4800U, 4778U, 
    1747U, 6203U, 1937U, 2707U, 1738U, 6269U, 6678U, 1206U, 
    6026U, 6524U, 6053U, 6824U, 1246U, 6513U, 6501U, 6653U, 
    2646U, 6803U, 2578U, 6833U, 3882U, 5494U, 5480U, 3875U, 
    5487U, 5740U, 4010U, 5066U, 5059U, 5073U, 5080U, 6260U, 
    4619U, 1978U, 4603U, 1870U, 4611U, 1970U, 4595U, 1862U, 
    4722U, 4714U, 2726U, 2718U, 6121U, 6111U, 6101U, 6091U, 
    6141U, 6131U, 7425U, 7435U, 6151U, 6164U, 7445U, 7455U, 
    6177U, 6190U, 1457U, 894U, 4068U, 528U, 1317U, 7122U, 
    4132U, 7195U, 3217U, 5225U, 293U, 9U, 2639U, 258U, 
    0U, 5200U, 5232U, 2528U, 6795U, 1218U, 2991U, 3208U, 
    4907U, 4916U, 6224U, 6237U, 5758U, 4364U, 5965U, 2436U, 
    4274U, 4284U, 2027U, 2042U, 4231U, 4263U, 7157U, 7183U, 
    7169U, 1986U, 2014U, 1999U, 1584U, 3433U, 4461U, 7333U, 
    4485U, 7357U, 5765U, 1779U, 1769U, 5290U, 6397U, 2099U, 
    5587U, 5567U, 6425U, 6404U, 5621U, 5652U, 5638U, 6008U, 
    7574U, 2470U, 7545U, 2452U, 5117U, 4822U, 2280U, 3888U, 
    5843U, 4533U, 5850U, 4320U, 5835U, 4525U, 4312U, 266U, 
    2768U, 2760U, 2752U, 6717U, 5535U, 6587U, 6632U, 6750U, 
    5308U, 2108U, 1275U, 2405U, 2241U, 1485U, 901U, 4096U, 
    7129U, 4139U, 534U, 6725U, 5209U, 5447U, 5463U, 7489U, 
    2170U, 2417U, 6322U, 4730U, 4771U, 4747U, 4759U, 1464U, 
    4075U, 1440U, 4051U, 7236U, 4410U, 4242U, 4210U, 1562U, 
    4110U, 1673U, 5705U, 5667U, 7316U, 4444U, 7340U, 4468U, 
    7411U, 7418U, 4578U, 5150U, 1724U, 4627U, 5544U, 2366U, 
    2671U, 2302U, 2688U, 7399U, 6301U, 3896U, 3813U, 2893U, 
    2842U, 2776U, 2917U, 2862U, 2792U, 6782U, 823U, 2808U, 
    2826U, 2882U, 2817U, 2834U, 5371U, 4639U, 5321U, 437U, 
    174U, 360U, 141U, 373U, 5501U, 2905U, 2852U, 2784U, 
    2929U, 2872U, 2800U, 2243U, 2407U, 4187U, 5761U, 1409U, 
    3007U, 3322U, 1647U, 319U, 1108U, 310U, 604U, 833U, 
    3314U, 734U, 611U, 843U, 3329U, 744U, 4195U, 515U, 
    5292U, 1732U, 2535U, 7552U, 1113U, 5860U, 7564U, 3897U, 
    7541U, 5244U, 3128U, 3350U, 2189U, 6487U, 3137U, 6494U, 
    3380U, 5831U, 2541U, 7557U, 5866U, 7568U, 165U, 1538U, 
    7292U, 1422U, 3498U, 6878U, 4987U, 5916U, 970U, 5261U, 
    3698U, 7024U, 2077U, 3536U, 6902U, 6351U, 3740U, 7052U, 
    2148U, 3578U, 6930U, 6465U, 3782U, 7080U, 2206U, 3620U, 
    6958U, 5191U, 283U, 557U, 1662U, 4546U, 248U, 7218U, 
    1297U, 4392U, 4033U, 3660U, 6986U, 1621U, 876U, 3462U, 
    6854U, 3180U, 4294U, 2742U, 154U, 478U, 1061U, 1550U, 
    7304U, 999U, 1431U, 3510U, 6890U, 4998U, 5927U, 980U, 
    5272U, 3712U, 7038U, 2088U, 3550U, 6916U, 6362U, 3754U, 
    7066U, 2159U, 3592U, 6944U, 6476U, 3796U, 7094U, 2217U, 
    3634U, 6972U, 1017U, 5009U, 1152U, 4938U, 1121U, 1096U, 
    7227U, 1307U, 4401U, 7465U, 4042U, 3672U, 6998U, 3422U, 
    5022U, 1166U, 5046U, 1192U, 1085U, 885U, 3474U, 6866U, 
    3194U, 4303U, 1073U, 1008U, 1038U, 488U, 1516U, 7270U, 
    1406U, 4967U, 5896U, 5241U, 2057U, 6331U, 2128U, 6445U, 
    2186U, 7115U, 5184U, 275U, 185U, 205U, 6547U, 4540U, 
    240U, 954U, 7202U, 4376U, 4017U, 7481U, 7474U, 1610U, 
    5035U, 1180U, 4925U, 6709U, 860U, 3154U, 2734U, 386U, 
    196U, 217U, 1526U, 7280U, 1413U, 3486U, 5087U, 7503U, 
    4976U, 5905U, 5250U, 3684U, 2066U, 3522U, 6340U, 3726U, 
    2137U, 3564U, 6454U, 3768U, 2195U, 3606U, 547U, 1651U, 
    961U, 7209U, 4383U, 4024U, 3648U, 3411U, 867U, 3450U, 
    3166U, 395U, 1049U, 990U, 1027U, 416U, 406U, 5938U, 
    427U, 4953U, 1137U, 6283U, 467U, 5781U, 4879U, 3091U, 
    3274U, 1914U, 1901U, 128U, 4830U, 774U, 3028U, 630U, 
    567U, 3231U, 694U, 111U, 1878U, 1925U, 5771U, 796U, 
    658U, 581U, 714U, 354U, 336U, 4849U, 3052U, 3247U, 
    473U, 3283U, 119U, 301U, 345U, 100U, 455U, 4859U, 
    3065U, 3256U, 504U, 4889U, 3104U, 3291U, 1890U, 461U, 
    4869U, 3078U, 3265U, 523U, 4898U, 3116U, 3299U, 7205U, 
    3147U, 3397U, 4379U, 3021U, 3343U, 7581U, 4020U, 3014U, 
    6645U, 330U, 5527U, 325U, 818U, 7535U, 852U, 3366U, 
    753U, 1292U, 6791U, 448U, 595U, 227U, 3443U, 58U, 
    5283U, 91U, 6649U, 3390U, 4570U, 4574U, 3982U, 3225U, 
    686U, 3878U, 3336U, 5483U, 5874U, 3372U, 3359U, 2963U, 
    34U, 4694U, 67U, 2952U, 617U, 4683U, 761U, 7010U, 
    2941U, 4672U, 509U, 2973U, 46U, 4704U, 79U, 26U, 
    785U, 3040U, 644U, 574U, 3239U, 704U, 1892U, 807U, 
    672U, 588U, 724U, 234U, 4839U, 863U, 3000U, 3307U, 
    498U, 18U, 3404U, 4754U, 6282U, 6790U, 133U, 317U, 
    5530U, 5679U, 
};

static inline void InitColossusMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(ColossusDescs.Insts, ColossusInstrNameIndices, ColossusInstrNameData, nullptr, nullptr, 706);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct ColossusGenInstrInfo : public TargetInstrInfo {
  explicit ColossusGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~ColossusGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const ColossusInstrTable ColossusDescs;
extern const unsigned ColossusInstrNameIndices[];
extern const char ColossusInstrNameData[];
ColossusGenInstrInfo::ColossusGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(ColossusDescs.Insts, ColossusInstrNameIndices, ColossusInstrNameData, nullptr, nullptr, 706);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace Colossus {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace Colossus
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace Colossus {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace Colossus
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace Colossus {
namespace OpTypes {
enum OperandType {
  CallOperand = 0,
  CoissueFlag = 1,
  LabelOperand = 2,
  MEMri = 3,
  MEMrr = 4,
  MEMrri = 5,
  MEMrrr = 6,
  Rel8Operand = 7,
  Rel16Operand = 8,
  Rel19S2Operand = 9,
  Rel20Operand = 10,
  Rel21Operand = 11,
  RunOperand = 12,
  f16imm = 13,
  f32imm = 14,
  f64imm = 15,
  fp32imm12iz = 16,
  fp32imm12zi = 17,
  i1imm = 18,
  i8imm = 19,
  i16imm = 20,
  i32imm = 21,
  i64imm = 22,
  imm1zi = 23,
  imm2zi = 24,
  imm3zi = 25,
  imm4zi = 26,
  imm6zi = 27,
  imm7zi = 28,
  imm8si = 29,
  imm8zi = 30,
  imm11si = 31,
  imm12iz = 32,
  imm12zi = 33,
  imm13zi = 34,
  imm16si = 35,
  imm16zi = 36,
  imm19zi = 37,
  imm20zi = 38,
  ptype0 = 39,
  ptype1 = 40,
  ptype2 = 41,
  ptype3 = 42,
  ptype4 = 43,
  ptype5 = 44,
  type0 = 45,
  type1 = 46,
  type2 = 47,
  type3 = 48,
  type4 = 49,
  type5 = 50,
  untyped_imm_0 = 51,
  ACCOperand = 52,
  ACCPairOperand = 53,
  ARPairOperand = 54,
  ARQuadOperand = 55,
  BroadcastLowerOperand = 56,
  BroadcastOperand = 57,
  BroadcastUpperOperand = 58,
  ACC = 59,
  ACCPair = 60,
  ACCQuad = 61,
  AR = 62,
  AROctad = 63,
  ARPair = 64,
  ARQuad = 65,
  MR = 66,
  MRPair = 67,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace Colossus
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace Colossus {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* INIT_UNDEF */
    13,
    /* SUBREG_TO_REG */
    14,
    /* COPY_TO_REGCLASS */
    18,
    /* DBG_VALUE */
    21,
    /* DBG_VALUE_LIST */
    21,
    /* DBG_INSTR_REF */
    21,
    /* DBG_PHI */
    21,
    /* DBG_LABEL */
    21,
    /* REG_SEQUENCE */
    22,
    /* COPY */
    24,
    /* BUNDLE */
    26,
    /* LIFETIME_START */
    26,
    /* LIFETIME_END */
    27,
    /* PSEUDO_PROBE */
    28,
    /* ARITH_FENCE */
    32,
    /* STACKMAP */
    34,
    /* FENTRY_CALL */
    36,
    /* PATCHPOINT */
    36,
    /* LOAD_STACK_GUARD */
    42,
    /* PREALLOCATED_SETUP */
    43,
    /* PREALLOCATED_ARG */
    44,
    /* STATEPOINT */
    47,
    /* LOCAL_ESCAPE */
    47,
    /* FAULTING_OP */
    49,
    /* PATCHABLE_OP */
    50,
    /* PATCHABLE_FUNCTION_ENTER */
    50,
    /* PATCHABLE_RET */
    50,
    /* PATCHABLE_FUNCTION_EXIT */
    50,
    /* PATCHABLE_TAIL_CALL */
    50,
    /* PATCHABLE_EVENT_CALL */
    50,
    /* PATCHABLE_TYPED_EVENT_CALL */
    52,
    /* ICALL_BRANCH_FUNNEL */
    55,
    /* FAKE_USE */
    55,
    /* MEMBARRIER */
    55,
    /* JUMP_TABLE_DEBUG_INFO */
    55,
    /* CONVERGENCECTRL_ENTRY */
    56,
    /* CONVERGENCECTRL_ANCHOR */
    57,
    /* CONVERGENCECTRL_LOOP */
    58,
    /* CONVERGENCECTRL_GLUE */
    60,
    /* G_ASSERT_SEXT */
    61,
    /* G_ASSERT_ZEXT */
    64,
    /* G_ASSERT_ALIGN */
    67,
    /* G_ADD */
    70,
    /* G_SUB */
    73,
    /* G_MUL */
    76,
    /* G_SDIV */
    79,
    /* G_UDIV */
    82,
    /* G_SREM */
    85,
    /* G_UREM */
    88,
    /* G_SDIVREM */
    91,
    /* G_UDIVREM */
    95,
    /* G_AND */
    99,
    /* G_OR */
    102,
    /* G_XOR */
    105,
    /* G_ABDS */
    108,
    /* G_ABDU */
    111,
    /* G_IMPLICIT_DEF */
    114,
    /* G_PHI */
    115,
    /* G_FRAME_INDEX */
    116,
    /* G_GLOBAL_VALUE */
    118,
    /* G_PTRAUTH_GLOBAL_VALUE */
    120,
    /* G_CONSTANT_POOL */
    125,
    /* G_EXTRACT */
    127,
    /* G_UNMERGE_VALUES */
    130,
    /* G_INSERT */
    132,
    /* G_MERGE_VALUES */
    136,
    /* G_BUILD_VECTOR */
    138,
    /* G_BUILD_VECTOR_TRUNC */
    140,
    /* G_CONCAT_VECTORS */
    142,
    /* G_PTRTOINT */
    144,
    /* G_INTTOPTR */
    146,
    /* G_BITCAST */
    148,
    /* G_FREEZE */
    150,
    /* G_CONSTANT_FOLD_BARRIER */
    152,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    154,
    /* G_INTRINSIC_TRUNC */
    157,
    /* G_INTRINSIC_ROUND */
    159,
    /* G_INTRINSIC_LRINT */
    161,
    /* G_INTRINSIC_LLRINT */
    163,
    /* G_INTRINSIC_ROUNDEVEN */
    165,
    /* G_READCYCLECOUNTER */
    167,
    /* G_READSTEADYCOUNTER */
    168,
    /* G_LOAD */
    169,
    /* G_SEXTLOAD */
    171,
    /* G_ZEXTLOAD */
    173,
    /* G_INDEXED_LOAD */
    175,
    /* G_INDEXED_SEXTLOAD */
    180,
    /* G_INDEXED_ZEXTLOAD */
    185,
    /* G_STORE */
    190,
    /* G_INDEXED_STORE */
    192,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    197,
    /* G_ATOMIC_CMPXCHG */
    202,
    /* G_ATOMICRMW_XCHG */
    206,
    /* G_ATOMICRMW_ADD */
    209,
    /* G_ATOMICRMW_SUB */
    212,
    /* G_ATOMICRMW_AND */
    215,
    /* G_ATOMICRMW_NAND */
    218,
    /* G_ATOMICRMW_OR */
    221,
    /* G_ATOMICRMW_XOR */
    224,
    /* G_ATOMICRMW_MAX */
    227,
    /* G_ATOMICRMW_MIN */
    230,
    /* G_ATOMICRMW_UMAX */
    233,
    /* G_ATOMICRMW_UMIN */
    236,
    /* G_ATOMICRMW_FADD */
    239,
    /* G_ATOMICRMW_FSUB */
    242,
    /* G_ATOMICRMW_FMAX */
    245,
    /* G_ATOMICRMW_FMIN */
    248,
    /* G_ATOMICRMW_UINC_WRAP */
    251,
    /* G_ATOMICRMW_UDEC_WRAP */
    254,
    /* G_ATOMICRMW_USUB_COND */
    257,
    /* G_ATOMICRMW_USUB_SAT */
    260,
    /* G_FENCE */
    263,
    /* G_PREFETCH */
    265,
    /* G_BRCOND */
    269,
    /* G_BRINDIRECT */
    271,
    /* G_INVOKE_REGION_START */
    272,
    /* G_INTRINSIC */
    272,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    273,
    /* G_INTRINSIC_CONVERGENT */
    274,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    275,
    /* G_ANYEXT */
    276,
    /* G_TRUNC */
    278,
    /* G_CONSTANT */
    280,
    /* G_FCONSTANT */
    282,
    /* G_VASTART */
    284,
    /* G_VAARG */
    285,
    /* G_SEXT */
    288,
    /* G_SEXT_INREG */
    290,
    /* G_ZEXT */
    293,
    /* G_SHL */
    295,
    /* G_LSHR */
    298,
    /* G_ASHR */
    301,
    /* G_FSHL */
    304,
    /* G_FSHR */
    308,
    /* G_ROTR */
    312,
    /* G_ROTL */
    315,
    /* G_ICMP */
    318,
    /* G_FCMP */
    322,
    /* G_SCMP */
    326,
    /* G_UCMP */
    329,
    /* G_SELECT */
    332,
    /* G_UADDO */
    336,
    /* G_UADDE */
    340,
    /* G_USUBO */
    345,
    /* G_USUBE */
    349,
    /* G_SADDO */
    354,
    /* G_SADDE */
    358,
    /* G_SSUBO */
    363,
    /* G_SSUBE */
    367,
    /* G_UMULO */
    372,
    /* G_SMULO */
    376,
    /* G_UMULH */
    380,
    /* G_SMULH */
    383,
    /* G_UADDSAT */
    386,
    /* G_SADDSAT */
    389,
    /* G_USUBSAT */
    392,
    /* G_SSUBSAT */
    395,
    /* G_USHLSAT */
    398,
    /* G_SSHLSAT */
    401,
    /* G_SMULFIX */
    404,
    /* G_UMULFIX */
    408,
    /* G_SMULFIXSAT */
    412,
    /* G_UMULFIXSAT */
    416,
    /* G_SDIVFIX */
    420,
    /* G_UDIVFIX */
    424,
    /* G_SDIVFIXSAT */
    428,
    /* G_UDIVFIXSAT */
    432,
    /* G_FADD */
    436,
    /* G_FSUB */
    439,
    /* G_FMUL */
    442,
    /* G_FMA */
    445,
    /* G_FMAD */
    449,
    /* G_FDIV */
    453,
    /* G_FREM */
    456,
    /* G_FPOW */
    459,
    /* G_FPOWI */
    462,
    /* G_FEXP */
    465,
    /* G_FEXP2 */
    467,
    /* G_FEXP10 */
    469,
    /* G_FLOG */
    471,
    /* G_FLOG2 */
    473,
    /* G_FLOG10 */
    475,
    /* G_FLDEXP */
    477,
    /* G_FFREXP */
    480,
    /* G_FNEG */
    483,
    /* G_FPEXT */
    485,
    /* G_FPTRUNC */
    487,
    /* G_FPTOSI */
    489,
    /* G_FPTOUI */
    491,
    /* G_SITOFP */
    493,
    /* G_UITOFP */
    495,
    /* G_FPTOSI_SAT */
    497,
    /* G_FPTOUI_SAT */
    499,
    /* G_FABS */
    501,
    /* G_FCOPYSIGN */
    503,
    /* G_IS_FPCLASS */
    506,
    /* G_FCANONICALIZE */
    509,
    /* G_FMINNUM */
    511,
    /* G_FMAXNUM */
    514,
    /* G_FMINNUM_IEEE */
    517,
    /* G_FMAXNUM_IEEE */
    520,
    /* G_FMINIMUM */
    523,
    /* G_FMAXIMUM */
    526,
    /* G_GET_FPENV */
    529,
    /* G_SET_FPENV */
    530,
    /* G_RESET_FPENV */
    531,
    /* G_GET_FPMODE */
    531,
    /* G_SET_FPMODE */
    532,
    /* G_RESET_FPMODE */
    533,
    /* G_PTR_ADD */
    533,
    /* G_PTRMASK */
    536,
    /* G_SMIN */
    539,
    /* G_SMAX */
    542,
    /* G_UMIN */
    545,
    /* G_UMAX */
    548,
    /* G_ABS */
    551,
    /* G_LROUND */
    553,
    /* G_LLROUND */
    555,
    /* G_BR */
    557,
    /* G_BRJT */
    558,
    /* G_VSCALE */
    561,
    /* G_INSERT_SUBVECTOR */
    563,
    /* G_EXTRACT_SUBVECTOR */
    567,
    /* G_INSERT_VECTOR_ELT */
    570,
    /* G_EXTRACT_VECTOR_ELT */
    574,
    /* G_SHUFFLE_VECTOR */
    577,
    /* G_SPLAT_VECTOR */
    581,
    /* G_STEP_VECTOR */
    583,
    /* G_VECTOR_COMPRESS */
    585,
    /* G_CTTZ */
    589,
    /* G_CTTZ_ZERO_UNDEF */
    591,
    /* G_CTLZ */
    593,
    /* G_CTLZ_ZERO_UNDEF */
    595,
    /* G_CTPOP */
    597,
    /* G_BSWAP */
    599,
    /* G_BITREVERSE */
    601,
    /* G_FCEIL */
    603,
    /* G_FCOS */
    605,
    /* G_FSIN */
    607,
    /* G_FSINCOS */
    609,
    /* G_FTAN */
    612,
    /* G_FACOS */
    614,
    /* G_FASIN */
    616,
    /* G_FATAN */
    618,
    /* G_FATAN2 */
    620,
    /* G_FCOSH */
    623,
    /* G_FSINH */
    625,
    /* G_FTANH */
    627,
    /* G_FSQRT */
    629,
    /* G_FFLOOR */
    631,
    /* G_FRINT */
    633,
    /* G_FNEARBYINT */
    635,
    /* G_ADDRSPACE_CAST */
    637,
    /* G_BLOCK_ADDR */
    639,
    /* G_JUMP_TABLE */
    641,
    /* G_DYN_STACKALLOC */
    643,
    /* G_STACKSAVE */
    646,
    /* G_STACKRESTORE */
    647,
    /* G_STRICT_FADD */
    648,
    /* G_STRICT_FSUB */
    651,
    /* G_STRICT_FMUL */
    654,
    /* G_STRICT_FDIV */
    657,
    /* G_STRICT_FREM */
    660,
    /* G_STRICT_FMA */
    663,
    /* G_STRICT_FSQRT */
    667,
    /* G_STRICT_FLDEXP */
    669,
    /* G_READ_REGISTER */
    672,
    /* G_WRITE_REGISTER */
    674,
    /* G_MEMCPY */
    676,
    /* G_MEMCPY_INLINE */
    680,
    /* G_MEMMOVE */
    683,
    /* G_MEMSET */
    687,
    /* G_BZERO */
    691,
    /* G_TRAP */
    694,
    /* G_DEBUGTRAP */
    694,
    /* G_UBSANTRAP */
    694,
    /* G_VECREDUCE_SEQ_FADD */
    695,
    /* G_VECREDUCE_SEQ_FMUL */
    698,
    /* G_VECREDUCE_FADD */
    701,
    /* G_VECREDUCE_FMUL */
    703,
    /* G_VECREDUCE_FMAX */
    705,
    /* G_VECREDUCE_FMIN */
    707,
    /* G_VECREDUCE_FMAXIMUM */
    709,
    /* G_VECREDUCE_FMINIMUM */
    711,
    /* G_VECREDUCE_ADD */
    713,
    /* G_VECREDUCE_MUL */
    715,
    /* G_VECREDUCE_AND */
    717,
    /* G_VECREDUCE_OR */
    719,
    /* G_VECREDUCE_XOR */
    721,
    /* G_VECREDUCE_SMAX */
    723,
    /* G_VECREDUCE_SMIN */
    725,
    /* G_VECREDUCE_UMAX */
    727,
    /* G_VECREDUCE_UMIN */
    729,
    /* G_SBFX */
    731,
    /* G_UBFX */
    735,
    /* ADJCALLSTACKDOWN */
    739,
    /* ADJCALLSTACKUP */
    741,
    /* CALLIND */
    743,
    /* CALL_PSEUDO */
    745,
    /* CLOOP_BEGIN_TERMINATOR */
    746,
    /* CLOOP_BEGIN_VALUE */
    748,
    /* CLOOP_END_BRANCH */
    751,
    /* CLOOP_END_VALUE */
    754,
    /* CLOOP_GUARD_BRANCH */
    757,
    /* FRAME_INDEX */
    760,
    /* FRAME_TO_ARGS_OFFSET */
    763,
    /* ICALL */
    764,
    /* LABEL */
    766,
    /* LD32_ACC_FI */
    767,
    /* LD32_A_FI */
    770,
    /* LD32_FI */
    773,
    /* LD64_ACC_FI */
    776,
    /* LD64_A_FI */
    779,
    /* LD64_FI */
    782,
    /* LDCONST */
    785,
    /* LDCONST_A */
    787,
    /* LDS16_FI */
    789,
    /* LDS8_FI */
    792,
    /* LDZ16_A_FI */
    795,
    /* LDZ16_FI */
    798,
    /* LDZ8_FI */
    801,
    /* MEM_BARRIER */
    804,
    /* RTN_PSEUDO */
    804,
    /* RTN_REG_HOLDER */
    804,
    /* SELECT_F16 */
    804,
    /* SELECT_F32 */
    808,
    /* SELECT_V2F16 */
    812,
    /* SELECT_V2F32 */
    816,
    /* SELECT_V4F16 */
    820,
    /* SETLR */
    824,
    /* ST32_ACC_FI */
    825,
    /* ST32_A_FI */
    828,
    /* ST32_FI */
    831,
    /* ST64_ACC_FI */
    834,
    /* ST64_A_FI */
    837,
    /* ST64_FI */
    840,
    /* STACKRESTORE */
    843,
    /* STACKSAVE */
    843,
    /* SUB_IMM */
    843,
    /* ABS */
    847,
    /* ADD */
    850,
    /* ADD_SI */
    854,
    /* ADD_ZI */
    858,
    /* AND */
    862,
    /* AND64 */
    866,
    /* ANDC */
    870,
    /* ANDC64 */
    874,
    /* ANDC_A */
    878,
    /* ANDC_IZ_A */
    882,
    /* ANDC_ZI */
    886,
    /* ANDC_ZI_A */
    890,
    /* AND_A */
    894,
    /* AND_IZ_A */
    898,
    /* AND_ZI */
    902,
    /* AND_ZI_A */
    906,
    /* ATOM */
    910,
    /* BITREV8 */
    913,
    /* BR */
    916,
    /* BRIND */
    918,
    /* BRNEG */
    920,
    /* BRNZ */
    923,
    /* BRNZDEC */
    926,
    /* BRPOS */
    930,
    /* BRZ */
    933,
    /* CALL */
    936,
    /* CLZ */
    939,
    /* CMPEQ */
    942,
    /* CMPEQ_SI */
    946,
    /* CMPEQ_ZI */
    950,
    /* CMPNE */
    954,
    /* CMPSLT */
    958,
    /* CMPSLT_SI */
    962,
    /* CMPULT */
    966,
    /* CMPULT_ZI */
    970,
    /* CMS */
    974,
    /* EXITNEG */
    977,
    /* EXITNZ */
    979,
    /* EXITPOS */
    981,
    /* EXITZ */
    983,
    /* F16TOF32 */
    985,
    /* F16V2ABSADD */
    988,
    /* F16V2ABSMAX */
    992,
    /* F16V2ADD */
    996,
    /* F16V2ADD_BL */
    1000,
    /* F16V2ADD_BU */
    1004,
    /* F16V2CLAMP */
    1008,
    /* F16V2CLASS */
    1012,
    /* F16V2CMAC */
    1015,
    /* F16V2CMPEQ */
    1018,
    /* F16V2CMPEQ_BL */
    1022,
    /* F16V2CMPEQ_BU */
    1026,
    /* F16V2CMPGE */
    1030,
    /* F16V2CMPGE_BL */
    1034,
    /* F16V2CMPGE_BU */
    1038,
    /* F16V2CMPGT */
    1042,
    /* F16V2CMPGT_BL */
    1046,
    /* F16V2CMPGT_BU */
    1050,
    /* F16V2CMPLE */
    1054,
    /* F16V2CMPLE_BL */
    1058,
    /* F16V2CMPLE_BU */
    1062,
    /* F16V2CMPLT */
    1066,
    /* F16V2CMPLT_BL */
    1070,
    /* F16V2CMPLT_BU */
    1074,
    /* F16V2CMPNE */
    1078,
    /* F16V2CMPNE_BL */
    1082,
    /* F16V2CMPNE_BU */
    1086,
    /* F16V2EXP */
    1090,
    /* F16V2EXP2 */
    1093,
    /* F16V2GINA */
    1096,
    /* F16V2GRAND */
    1100,
    /* F16V2LN */
    1102,
    /* F16V2LOG2 */
    1105,
    /* F16V2MAX */
    1108,
    /* F16V2MAXC */
    1112,
    /* F16V2MIN */
    1115,
    /* F16V2MUL */
    1119,
    /* F16V2MUL_BL */
    1123,
    /* F16V2MUL_BU */
    1127,
    /* F16V2SIGMOID */
    1131,
    /* F16V2SUB */
    1134,
    /* F16V2SUB_BL */
    1138,
    /* F16V2SUB_BU */
    1142,
    /* F16V2SUFROMUI */
    1146,
    /* F16V2SUM */
    1149,
    /* F16V2TANH */
    1152,
    /* F16V2TOF32 */
    1155,
    /* F16V2TOF8 */
    1158,
    /* F16V4ABSACC */
    1161,
    /* F16V4ABSADD */
    1163,
    /* F16V4ABSMAX */
    1167,
    /* F16V4ACC */
    1171,
    /* F16V4ADD */
    1173,
    /* F16V4ADD_BL */
    1177,
    /* F16V4ADD_BU */
    1181,
    /* F16V4CLAMP */
    1185,
    /* F16V4CLASS */
    1189,
    /* F16V4CMAC */
    1192,
    /* F16V4CMPEQ */
    1195,
    /* F16V4CMPEQ_BL */
    1199,
    /* F16V4CMPEQ_BU */
    1203,
    /* F16V4CMPGE */
    1207,
    /* F16V4CMPGE_BL */
    1211,
    /* F16V4CMPGE_BU */
    1215,
    /* F16V4CMPGT */
    1219,
    /* F16V4CMPGT_BL */
    1223,
    /* F16V4CMPGT_BU */
    1227,
    /* F16V4CMPLE */
    1231,
    /* F16V4CMPLE_BL */
    1235,
    /* F16V4CMPLE_BU */
    1239,
    /* F16V4CMPLT */
    1243,
    /* F16V4CMPLT_BL */
    1247,
    /* F16V4CMPLT_BU */
    1251,
    /* F16V4CMPNE */
    1255,
    /* F16V4CMPNE_BL */
    1259,
    /* F16V4CMPNE_BU */
    1263,
    /* F16V4GACC */
    1267,
    /* F16V4HIHOAMP */
    1269,
    /* F16V4HIHOSLIC */
    1274,
    /* F16V4HIHOV4AMP */
    1279,
    /* F16V4HIHOV4SLIC */
    1284,
    /* F16V4ISTACC */
    1289,
    /* F16V4MAX */
    1294,
    /* F16V4MAXC */
    1298,
    /* F16V4MIN */
    1301,
    /* F16V4MIX */
    1305,
    /* F16V4MUL */
    1309,
    /* F16V4MUL_BL */
    1313,
    /* F16V4MUL_BU */
    1317,
    /* F16V4RMASK */
    1321,
    /* F16V4SIHOAMP */
    1325,
    /* F16V4SIHOSLIC */
    1330,
    /* F16V4SISOAMP */
    1335,
    /* F16V4SISOSLIC */
    1340,
    /* F16V4STACC */
    1345,
    /* F16V4SUB */
    1348,
    /* F16V4SUB_BL */
    1352,
    /* F16V4SUB_BU */
    1356,
    /* F16V4SUFROMUI */
    1360,
    /* F16V4SUM */
    1363,
    /* F16V8ABSACC */
    1366,
    /* F16V8ACC */
    1368,
    /* F16V8SQACC */
    1370,
    /* F16V8TOF8 */
    1372,
    /* F32ABSADD */
    1375,
    /* F32ABSMAX */
    1379,
    /* F32ADD */
    1383,
    /* F32CLAMP */
    1387,
    /* F32CLASS */
    1391,
    /* F32CMPEQ */
    1394,
    /* F32CMPGE */
    1398,
    /* F32CMPGT */
    1402,
    /* F32CMPLE */
    1406,
    /* F32CMPLT */
    1410,
    /* F32CMPNE */
    1414,
    /* F32DIV */
    1418,
    /* F32EXP */
    1422,
    /* F32EXP2 */
    1425,
    /* F32FROMI32 */
    1428,
    /* F32FROMUI32 */
    1431,
    /* F32INT */
    1434,
    /* F32LN */
    1438,
    /* F32LOG2 */
    1441,
    /* F32MAC */
    1444,
    /* F32MAX */
    1447,
    /* F32MIN */
    1451,
    /* F32MUL */
    1455,
    /* F32OORX */
    1459,
    /* F32OOX */
    1462,
    /* F32SIGMOID */
    1465,
    /* F32SISOAMP */
    1468,
    /* F32SISOSLIC */
    1473,
    /* F32SISOV2AMP */
    1478,
    /* F32SQRT */
    1483,
    /* F32SUB */
    1486,
    /* F32SUFROMUI */
    1490,
    /* F32TANH */
    1493,
    /* F32TOF16 */
    1496,
    /* F32TOI32 */
    1499,
    /* F32TOUI32 */
    1502,
    /* F32V2ABSADD */
    1505,
    /* F32V2ABSMAX */
    1509,
    /* F32V2ADD */
    1513,
    /* F32V2ADD_BL */
    1517,
    /* F32V2AOP */
    1521,
    /* F32V2AXPY */
    1525,
    /* F32V2CLAMP */
    1529,
    /* F32V2CLASS */
    1533,
    /* F32V2CMPEQ */
    1536,
    /* F32V2CMPEQ_BL */
    1540,
    /* F32V2CMPGE */
    1544,
    /* F32V2CMPGE_BL */
    1548,
    /* F32V2CMPGT */
    1552,
    /* F32V2CMPGT_BL */
    1556,
    /* F32V2CMPLE */
    1560,
    /* F32V2CMPLE_BL */
    1564,
    /* F32V2CMPLT */
    1568,
    /* F32V2CMPLT_BL */
    1572,
    /* F32V2CMPNE */
    1576,
    /* F32V2CMPNE_BL */
    1580,
    /* F32V2GINA */
    1584,
    /* F32V2GRAND */
    1588,
    /* F32V2MAC */
    1590,
    /* F32V2MAX */
    1593,
    /* F32V2MIN */
    1597,
    /* F32V2MUL */
    1601,
    /* F32V2MUL_BL */
    1605,
    /* F32V2RMASK */
    1609,
    /* F32V2SUB */
    1613,
    /* F32V2SUB_BL */
    1617,
    /* F32V2SUFROMUI */
    1621,
    /* F32V2TOF16 */
    1624,
    /* F32V4ABSACC */
    1627,
    /* F32V4ACC */
    1629,
    /* F32V4SQACC */
    1631,
    /* F32V4TOF16 */
    1633,
    /* F8V2TOF16 */
    1636,
    /* F8V4CLASS */
    1639,
    /* F8V4TOF16 */
    1642,
    /* F8V8HIHOV4AMP */
    1645,
    /* F8V8HIHOV4SLIC */
    1650,
    /* GET */
    1655,
    /* LD128 */
    1658,
    /* LD128PUTCS */
    1663,
    /* LD128STEP */
    1665,
    /* LD128STEP_SI */
    1671,
    /* LD128_ZI */
    1677,
    /* LD2X64PACE */
    1682,
    /* LD2XST64PACE */
    1689,
    /* LD32 */
    1696,
    /* LD32STEP */
    1701,
    /* LD32STEP_A */
    1707,
    /* LD32STEP_SI */
    1713,
    /* LD32STEP_SI_A */
    1719,
    /* LD32_A */
    1725,
    /* LD32_ZI */
    1730,
    /* LD32_ZI_A */
    1735,
    /* LD64A32 */
    1740,
    /* LD64A32PACE */
    1746,
    /* LD64B16PACE */
    1753,
    /* LD64PUTCS */
    1760,
    /* LD64STEP_A */
    1762,
    /* LD64STEP_SI_A */
    1768,
    /* LD64_A */
    1774,
    /* LD64_ZI_A */
    1779,
    /* LDB16 */
    1784,
    /* LDB16B16 */
    1789,
    /* LDB16STEP */
    1796,
    /* LDB16STEP_SI */
    1802,
    /* LDB16_ZI */
    1808,
    /* LDB8 */
    1813,
    /* LDB8_ZI */
    1818,
    /* LDD16A32 */
    1823,
    /* LDD16A64 */
    1830,
    /* LDD16B16 */
    1837,
    /* LDD16V2A32 */
    1844,
    /* LDS16 */
    1851,
    /* LDS16STEP */
    1856,
    /* LDS16STEP_SI */
    1862,
    /* LDS16_ZI */
    1868,
    /* LDS8 */
    1873,
    /* LDS8STEP */
    1878,
    /* LDS8STEP_SI */
    1884,
    /* LDS8_ZI */
    1890,
    /* LDST64PACE */
    1895,
    /* LDZ16 */
    1902,
    /* LDZ16STEP */
    1907,
    /* LDZ16STEP_SI */
    1913,
    /* LDZ16_ZI */
    1919,
    /* LDZ8 */
    1924,
    /* LDZ8STEP */
    1929,
    /* LDZ8STEP_SI */
    1935,
    /* LDZ8_ZI */
    1941,
    /* MAX */
    1946,
    /* MAX_SI */
    1950,
    /* MAX_ZI */
    1954,
    /* MIN */
    1958,
    /* MIN_SI */
    1962,
    /* MIN_ZI */
    1966,
    /* MOVZ */
    1970,
    /* MUL */
    1975,
    /* MUL_SI */
    1979,
    /* NOT */
    1983,
    /* NOT64 */
    1986,
    /* OR */
    1989,
    /* OR64 */
    1993,
    /* OR_A */
    1997,
    /* OR_IZ */
    2001,
    /* OR_IZ_A */
    2005,
    /* OR_ZI */
    2009,
    /* OR_ZI_A */
    2013,
    /* POPC */
    2017,
    /* PUT */
    2020,
    /* ROLL16 */
    2023,
    /* ROLL16_A */
    2027,
    /* ROLL32 */
    2031,
    /* ROLL8L */
    2035,
    /* ROLL8L_1 */
    2039,
    /* ROLL8R */
    2043,
    /* ROLL8R_1 */
    2047,
    /* RPT */
    2051,
    /* RPT_ZI */
    2054,
    /* RTN */
    2057,
    /* RUN */
    2059,
    /* RUNALL */
    2063,
    /* SETZI */
    2067,
    /* SETZI_A */
    2070,
    /* SHL */
    2073,
    /* SHL_ZI */
    2077,
    /* SHR */
    2081,
    /* SHRS */
    2085,
    /* SHRS_ZI */
    2089,
    /* SHR_ZI */
    2093,
    /* SHUF8X8HI */
    2097,
    /* SHUF8X8HI_1 */
    2101,
    /* SHUF8X8LO */
    2105,
    /* SHUF8X8LO_1 */
    2109,
    /* SORT4X16HI */
    2113,
    /* SORT4X16HI_A */
    2117,
    /* SORT4X16LO */
    2121,
    /* SORT4X16LO_A */
    2125,
    /* SORT4X16LO_BU */
    2129,
    /* SORT4X32HI */
    2133,
    /* SORT4X32LO */
    2137,
    /* SORT8 */
    2141,
    /* SORT8X8HI */
    2144,
    /* SORT8X8HI_1 */
    2148,
    /* SORT8X8LO */
    2152,
    /* SORT8X8LO_1 */
    2156,
    /* SORT8_1 */
    2160,
    /* ST32STEP_A */
    2163,
    /* ST32STEP_SI */
    2169,
    /* ST32STEP_SI_A */
    2175,
    /* ST32_A */
    2181,
    /* ST32_ZI */
    2186,
    /* ST32_ZI_A */
    2191,
    /* ST64PACE */
    2196,
    /* ST64STEP_A */
    2202,
    /* ST64STEP_SI_A */
    2208,
    /* ST64_A */
    2214,
    /* ST64_ZI_A */
    2219,
    /* STM32 */
    2224,
    /* STM32STEP */
    2228,
    /* SUB */
    2233,
    /* SUB_SI */
    2237,
    /* SUB_ZI */
    2241,
    /* SWAP8 */
    2245,
    /* SWAP8_1 */
    2248,
    /* TAPACK */
    2251,
    /* TRAP */
    2256,
    /* UGET */
    2258,
    /* UPUT */
    2261,
    /* URAND32 */
    2264,
    /* URAND64 */
    2266,
    /* XNOR */
    2268,
    /* XOR */
    2272,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* INIT_UNDEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_ABDS */
    type0, type0, type0, 
    /* G_ABDU */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_COND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_USUB_SAT */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FPTOSI_SAT */
    type0, type1, 
    /* G_FPTOUI_SAT */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type1, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_STEP_VECTOR */
    type0, -1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FSINCOS */
    type0, type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FATAN2 */
    type0, type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADJCALLSTACKDOWN */
    i32imm, i32imm, 
    /* ADJCALLSTACKUP */
    i32imm, i32imm, 
    /* CALLIND */
    MR, CoissueFlag, 
    /* CALL_PSEUDO */
    CallOperand, 
    /* CLOOP_BEGIN_TERMINATOR */
    MR, imm16zi, 
    /* CLOOP_BEGIN_VALUE */
    MR, MR, imm16zi, 
    /* CLOOP_END_BRANCH */
    MR, Rel19S2Operand, imm16zi, 
    /* CLOOP_END_VALUE */
    MR, MR, imm16zi, 
    /* CLOOP_GUARD_BRANCH */
    MR, Rel19S2Operand, imm16zi, 
    /* FRAME_INDEX */
    MR, MR, MR, 
    /* FRAME_TO_ARGS_OFFSET */
    MR, 
    /* ICALL */
    LabelOperand, CallOperand, 
    /* LABEL */
    CallOperand, 
    /* LD32_ACC_FI */
    ACC, MR, MR, 
    /* LD32_A_FI */
    AR, MR, MR, 
    /* LD32_FI */
    MR, MR, MR, 
    /* LD64_ACC_FI */
    ACCPair, MR, MR, 
    /* LD64_A_FI */
    ARPair, MR, MR, 
    /* LD64_FI */
    MRPair, MR, MR, 
    /* LDCONST */
    MR, i32imm, 
    /* LDCONST_A */
    AR, i32imm, 
    /* LDS16_FI */
    MR, MR, MR, 
    /* LDS8_FI */
    MR, MR, MR, 
    /* LDZ16_A_FI */
    AR, MR, MR, 
    /* LDZ16_FI */
    MR, MR, MR, 
    /* LDZ8_FI */
    MR, MR, MR, 
    /* MEM_BARRIER */
    /* RTN_PSEUDO */
    /* RTN_REG_HOLDER */
    /* SELECT_F16 */
    AR, MR, AR, AR, 
    /* SELECT_F32 */
    AR, MR, AR, AR, 
    /* SELECT_V2F16 */
    AR, MR, AR, AR, 
    /* SELECT_V2F32 */
    ARPairOperand, MR, ARPairOperand, ARPairOperand, 
    /* SELECT_V4F16 */
    ARPairOperand, MR, ARPairOperand, ARPairOperand, 
    /* SETLR */
    LabelOperand, 
    /* ST32_ACC_FI */
    ACC, MR, MR, 
    /* ST32_A_FI */
    AR, MR, MR, 
    /* ST32_FI */
    MR, MR, MR, 
    /* ST64_ACC_FI */
    ACCPair, MR, MR, 
    /* ST64_A_FI */
    ARPair, MR, MR, 
    /* ST64_FI */
    MRPair, MR, MR, 
    /* STACKRESTORE */
    /* STACKSAVE */
    /* SUB_IMM */
    MR, MR, imm16si, CoissueFlag, 
    /* ABS */
    MR, MR, CoissueFlag, 
    /* ADD */
    MR, MR, MR, CoissueFlag, 
    /* ADD_SI */
    MR, MR, imm16si, CoissueFlag, 
    /* ADD_ZI */
    MR, MR, imm16zi, CoissueFlag, 
    /* AND */
    MR, MR, MR, CoissueFlag, 
    /* AND64 */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* ANDC */
    MR, MR, MR, CoissueFlag, 
    /* ANDC64 */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* ANDC_A */
    AR, AR, AR, CoissueFlag, 
    /* ANDC_IZ_A */
    AR, AR, imm12iz, CoissueFlag, 
    /* ANDC_ZI */
    MR, MR, imm12zi, CoissueFlag, 
    /* ANDC_ZI_A */
    AR, AR, imm12zi, CoissueFlag, 
    /* AND_A */
    AR, AR, AR, CoissueFlag, 
    /* AND_IZ_A */
    AR, AR, imm12iz, CoissueFlag, 
    /* AND_ZI */
    MR, MR, imm12zi, CoissueFlag, 
    /* AND_ZI_A */
    AR, AR, imm12zi, CoissueFlag, 
    /* ATOM */
    MR, AR, CoissueFlag, 
    /* BITREV8 */
    MR, MR, CoissueFlag, 
    /* BR */
    Rel19S2Operand, CoissueFlag, 
    /* BRIND */
    MR, CoissueFlag, 
    /* BRNEG */
    MR, Rel19S2Operand, CoissueFlag, 
    /* BRNZ */
    MR, Rel19S2Operand, CoissueFlag, 
    /* BRNZDEC */
    MR, MR, Rel19S2Operand, CoissueFlag, 
    /* BRPOS */
    MR, Rel19S2Operand, CoissueFlag, 
    /* BRZ */
    MR, Rel19S2Operand, CoissueFlag, 
    /* CALL */
    MR, Rel19S2Operand, CoissueFlag, 
    /* CLZ */
    MR, MR, CoissueFlag, 
    /* CMPEQ */
    MR, MR, MR, CoissueFlag, 
    /* CMPEQ_SI */
    MR, MR, imm16si, CoissueFlag, 
    /* CMPEQ_ZI */
    MR, MR, imm16zi, CoissueFlag, 
    /* CMPNE */
    MR, MR, MR, CoissueFlag, 
    /* CMPSLT */
    MR, MR, MR, CoissueFlag, 
    /* CMPSLT_SI */
    MR, MR, imm16si, CoissueFlag, 
    /* CMPULT */
    MR, MR, MR, CoissueFlag, 
    /* CMPULT_ZI */
    MR, MR, Rel16Operand, CoissueFlag, 
    /* CMS */
    MR, MR, CoissueFlag, 
    /* EXITNEG */
    MR, CoissueFlag, 
    /* EXITNZ */
    MR, CoissueFlag, 
    /* EXITPOS */
    MR, CoissueFlag, 
    /* EXITZ */
    MR, CoissueFlag, 
    /* F16TOF32 */
    AR, AR, CoissueFlag, 
    /* F16V2ABSADD */
    AR, AR, AR, CoissueFlag, 
    /* F16V2ABSMAX */
    AR, AR, AR, CoissueFlag, 
    /* F16V2ADD */
    AR, AR, AR, CoissueFlag, 
    /* F16V2ADD_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2ADD_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2CLAMP */
    AR, AR, AR, CoissueFlag, 
    /* F16V2CLASS */
    AR, AR, CoissueFlag, 
    /* F16V2CMAC */
    AR, AR, CoissueFlag, 
    /* F16V2CMPEQ */
    AR, AR, AR, CoissueFlag, 
    /* F16V2CMPEQ_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2CMPEQ_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2CMPGE */
    AR, AR, AR, CoissueFlag, 
    /* F16V2CMPGE_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2CMPGE_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2CMPGT */
    AR, AR, AR, CoissueFlag, 
    /* F16V2CMPGT_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2CMPGT_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2CMPLE */
    AR, AR, AR, CoissueFlag, 
    /* F16V2CMPLE_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2CMPLE_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2CMPLT */
    AR, AR, AR, CoissueFlag, 
    /* F16V2CMPLT_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2CMPLT_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2CMPNE */
    AR, AR, AR, CoissueFlag, 
    /* F16V2CMPNE_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2CMPNE_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2EXP */
    AR, AR, CoissueFlag, 
    /* F16V2EXP2 */
    AR, AR, CoissueFlag, 
    /* F16V2GINA */
    AR, AR, imm12zi, CoissueFlag, 
    /* F16V2GRAND */
    AR, CoissueFlag, 
    /* F16V2LN */
    AR, AR, CoissueFlag, 
    /* F16V2LOG2 */
    AR, AR, CoissueFlag, 
    /* F16V2MAX */
    AR, AR, AR, CoissueFlag, 
    /* F16V2MAXC */
    AR, AR, CoissueFlag, 
    /* F16V2MIN */
    AR, AR, AR, CoissueFlag, 
    /* F16V2MUL */
    AR, AR, AR, CoissueFlag, 
    /* F16V2MUL_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2MUL_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2SIGMOID */
    AR, AR, CoissueFlag, 
    /* F16V2SUB */
    AR, AR, AR, CoissueFlag, 
    /* F16V2SUB_BL */
    AR, BroadcastLowerOperand, AR, CoissueFlag, 
    /* F16V2SUB_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* F16V2SUFROMUI */
    AR, AR, CoissueFlag, 
    /* F16V2SUM */
    AR, AR, CoissueFlag, 
    /* F16V2TANH */
    AR, AR, CoissueFlag, 
    /* F16V2TOF32 */
    ARPairOperand, AR, CoissueFlag, 
    /* F16V2TOF8 */
    AR, AR, CoissueFlag, 
    /* F16V4ABSACC */
    ARPairOperand, CoissueFlag, 
    /* F16V4ABSADD */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4ABSMAX */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4ACC */
    ARPairOperand, CoissueFlag, 
    /* F16V4ADD */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4ADD_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4ADD_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CLAMP */
    ARPairOperand, ARPairOperand, AR, CoissueFlag, 
    /* F16V4CLASS */
    AR, ARPairOperand, CoissueFlag, 
    /* F16V4CMAC */
    ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPEQ */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPEQ_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPEQ_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPGE */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPGE_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPGE_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPGT */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPGT_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPGT_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPLE */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPLE_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPLE_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPLT */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPLT_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPLT_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPNE */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPNE_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4CMPNE_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4GACC */
    ARPairOperand, CoissueFlag, 
    /* F16V4HIHOAMP */
    AR, ARPairOperand, AR, imm6zi, CoissueFlag, 
    /* F16V4HIHOSLIC */
    AR, ARPairOperand, AR, imm6zi, CoissueFlag, 
    /* F16V4HIHOV4AMP */
    ARPairOperand, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F16V4HIHOV4SLIC */
    ARPairOperand, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F16V4ISTACC */
    ARPairOperand, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F16V4MAX */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4MAXC */
    AR, ARPairOperand, CoissueFlag, 
    /* F16V4MIN */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4MIX */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4MUL */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4MUL_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4MUL_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4RMASK */
    ARPairOperand, ARPairOperand, AR, CoissueFlag, 
    /* F16V4SIHOAMP */
    AR, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F16V4SIHOSLIC */
    AR, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F16V4SISOAMP */
    ARPairOperand, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F16V4SISOSLIC */
    ARPairOperand, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F16V4STACC */
    ARPairOperand, imm8zi, CoissueFlag, 
    /* F16V4SUB */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4SUB_BL */
    ARPairOperand, BroadcastLowerOperand, ARPairOperand, CoissueFlag, 
    /* F16V4SUB_BU */
    ARPairOperand, BroadcastUpperOperand, ARPairOperand, CoissueFlag, 
    /* F16V4SUFROMUI */
    ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V4SUM */
    ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F16V8ABSACC */
    ARQuadOperand, CoissueFlag, 
    /* F16V8ACC */
    ARQuadOperand, CoissueFlag, 
    /* F16V8SQACC */
    ARQuadOperand, CoissueFlag, 
    /* F16V8TOF8 */
    ARPairOperand, ARQuadOperand, CoissueFlag, 
    /* F32ABSADD */
    AR, AR, AR, CoissueFlag, 
    /* F32ABSMAX */
    AR, AR, AR, CoissueFlag, 
    /* F32ADD */
    AR, AR, AR, CoissueFlag, 
    /* F32CLAMP */
    AR, AR, ARPairOperand, CoissueFlag, 
    /* F32CLASS */
    AR, AR, CoissueFlag, 
    /* F32CMPEQ */
    AR, AR, AR, CoissueFlag, 
    /* F32CMPGE */
    AR, AR, AR, CoissueFlag, 
    /* F32CMPGT */
    AR, AR, AR, CoissueFlag, 
    /* F32CMPLE */
    AR, AR, AR, CoissueFlag, 
    /* F32CMPLT */
    AR, AR, AR, CoissueFlag, 
    /* F32CMPNE */
    AR, AR, AR, CoissueFlag, 
    /* F32DIV */
    AR, AR, AR, CoissueFlag, 
    /* F32EXP */
    AR, AR, CoissueFlag, 
    /* F32EXP2 */
    AR, AR, CoissueFlag, 
    /* F32FROMI32 */
    AR, AR, CoissueFlag, 
    /* F32FROMUI32 */
    AR, AR, CoissueFlag, 
    /* F32INT */
    AR, AR, imm4zi, CoissueFlag, 
    /* F32LN */
    AR, AR, CoissueFlag, 
    /* F32LOG2 */
    AR, AR, CoissueFlag, 
    /* F32MAC */
    AR, AR, CoissueFlag, 
    /* F32MAX */
    AR, AR, AR, CoissueFlag, 
    /* F32MIN */
    AR, AR, AR, CoissueFlag, 
    /* F32MUL */
    AR, AR, AR, CoissueFlag, 
    /* F32OORX */
    AR, AR, CoissueFlag, 
    /* F32OOX */
    AR, AR, CoissueFlag, 
    /* F32SIGMOID */
    AR, AR, CoissueFlag, 
    /* F32SISOAMP */
    ARPairOperand, AR, ARPairOperand, imm6zi, CoissueFlag, 
    /* F32SISOSLIC */
    ARPairOperand, AR, ARPairOperand, imm6zi, CoissueFlag, 
    /* F32SISOV2AMP */
    ARPairOperand, AR, ARPairOperand, imm6zi, CoissueFlag, 
    /* F32SQRT */
    AR, AR, CoissueFlag, 
    /* F32SUB */
    AR, AR, AR, CoissueFlag, 
    /* F32SUFROMUI */
    AR, AR, CoissueFlag, 
    /* F32TANH */
    AR, AR, CoissueFlag, 
    /* F32TOF16 */
    AR, AR, CoissueFlag, 
    /* F32TOI32 */
    AR, AR, CoissueFlag, 
    /* F32TOUI32 */
    AR, AR, CoissueFlag, 
    /* F32V2ABSADD */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2ABSMAX */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2ADD */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2ADD_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2AOP */
    ARPairOperand, ARPairOperand, imm8zi, CoissueFlag, 
    /* F32V2AXPY */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CLAMP */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CLASS */
    AR, ARPairOperand, CoissueFlag, 
    /* F32V2CMPEQ */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPEQ_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPGE */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPGE_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPGT */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPGT_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPLE */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPLE_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPLT */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPLT_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPNE */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2CMPNE_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2GINA */
    ARPairOperand, ARPairOperand, imm12zi, CoissueFlag, 
    /* F32V2GRAND */
    ARPairOperand, CoissueFlag, 
    /* F32V2MAC */
    ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2MAX */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2MIN */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2MUL */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2MUL_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2RMASK */
    ARPairOperand, ARPairOperand, AR, CoissueFlag, 
    /* F32V2SUB */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2SUB_BL */
    ARPairOperand, BroadcastOperand, ARPairOperand, CoissueFlag, 
    /* F32V2SUFROMUI */
    ARPairOperand, ARPairOperand, CoissueFlag, 
    /* F32V2TOF16 */
    AR, ARPairOperand, CoissueFlag, 
    /* F32V4ABSACC */
    ARQuadOperand, CoissueFlag, 
    /* F32V4ACC */
    ARQuadOperand, CoissueFlag, 
    /* F32V4SQACC */
    ARQuadOperand, CoissueFlag, 
    /* F32V4TOF16 */
    ARPairOperand, ARQuadOperand, CoissueFlag, 
    /* F8V2TOF16 */
    AR, AR, CoissueFlag, 
    /* F8V4CLASS */
    AR, AR, CoissueFlag, 
    /* F8V4TOF16 */
    ARPairOperand, AR, CoissueFlag, 
    /* F8V8HIHOV4AMP */
    ARPairOperand, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* F8V8HIHOV4SLIC */
    ARPairOperand, ARPairOperand, ARPairOperand, imm6zi, CoissueFlag, 
    /* GET */
    MR, imm8zi, CoissueFlag, 
    /* LD128 */
    ARQuadOperand, MR, MR, MR, CoissueFlag, 
    /* LD128PUTCS */
    imm8zi, CoissueFlag, 
    /* LD128STEP */
    MR, ARQuadOperand, MR, MR, MR, CoissueFlag, 
    /* LD128STEP_SI */
    MR, ARQuadOperand, MR, MR, imm8si, CoissueFlag, 
    /* LD128_ZI */
    ARQuadOperand, MR, MR, i32imm, CoissueFlag, 
    /* LD2X64PACE */
    MRPair, ARPairOperand, ARPairOperand, MR, MRPair, imm4zi, CoissueFlag, 
    /* LD2XST64PACE */
    MRPair, ARQuadOperand, MR, MRPair, ARPairOperand, imm6zi, CoissueFlag, 
    /* LD32 */
    MR, MR, MR, MR, CoissueFlag, 
    /* LD32STEP */
    MR, MR, MR, MR, MR, CoissueFlag, 
    /* LD32STEP_A */
    MR, AR, MR, MR, MR, CoissueFlag, 
    /* LD32STEP_SI */
    MR, MR, MR, MR, imm8si, CoissueFlag, 
    /* LD32STEP_SI_A */
    MR, AR, MR, MR, imm8si, CoissueFlag, 
    /* LD32_A */
    AR, MR, MR, MR, CoissueFlag, 
    /* LD32_ZI */
    MR, MR, MR, i32imm, CoissueFlag, 
    /* LD32_ZI_A */
    AR, MR, MR, i32imm, CoissueFlag, 
    /* LD64A32 */
    MR, ARQuadOperand, MR, MR, MR, CoissueFlag, 
    /* LD64A32PACE */
    MRPair, ARPairOperand, AR, MR, MRPair, imm4zi, CoissueFlag, 
    /* LD64B16PACE */
    MRPair, ARPairOperand, AR, MR, MRPair, imm4zi, CoissueFlag, 
    /* LD64PUTCS */
    imm8zi, CoissueFlag, 
    /* LD64STEP_A */
    MR, ARPairOperand, MR, MR, MR, CoissueFlag, 
    /* LD64STEP_SI_A */
    MR, ARPairOperand, MR, MR, imm8si, CoissueFlag, 
    /* LD64_A */
    ARPairOperand, MR, MR, MR, CoissueFlag, 
    /* LD64_ZI_A */
    ARPairOperand, MR, MR, i32imm, CoissueFlag, 
    /* LDB16 */
    AR, MR, MR, MR, CoissueFlag, 
    /* LDB16B16 */
    MR, MR, ARPairOperand, MR, MR, MR, CoissueFlag, 
    /* LDB16STEP */
    MR, AR, MR, MR, MR, CoissueFlag, 
    /* LDB16STEP_SI */
    MR, AR, MR, MR, imm8si, CoissueFlag, 
    /* LDB16_ZI */
    AR, MR, MR, i32imm, CoissueFlag, 
    /* LDB8 */
    AR, MR, MR, MR, CoissueFlag, 
    /* LDB8_ZI */
    AR, MR, MR, i32imm, CoissueFlag, 
    /* LDD16A32 */
    MR, MR, AR, MR, MR, MR, CoissueFlag, 
    /* LDD16A64 */
    MR, MR, ARPairOperand, MR, MR, MR, CoissueFlag, 
    /* LDD16B16 */
    MR, MR, AR, MR, MR, MR, CoissueFlag, 
    /* LDD16V2A32 */
    MR, MR, AR, MR, MR, MR, CoissueFlag, 
    /* LDS16 */
    MR, MR, MR, MR, CoissueFlag, 
    /* LDS16STEP */
    MR, MR, MR, MR, MR, CoissueFlag, 
    /* LDS16STEP_SI */
    MR, MR, MR, MR, imm8si, CoissueFlag, 
    /* LDS16_ZI */
    MR, MR, MR, i32imm, CoissueFlag, 
    /* LDS8 */
    MR, MR, MR, MR, CoissueFlag, 
    /* LDS8STEP */
    MR, MR, MR, MR, MR, CoissueFlag, 
    /* LDS8STEP_SI */
    MR, MR, MR, MR, imm8si, CoissueFlag, 
    /* LDS8_ZI */
    MR, MR, MR, i32imm, CoissueFlag, 
    /* LDST64PACE */
    MRPair, ARPairOperand, MR, MRPair, ARPairOperand, imm4zi, CoissueFlag, 
    /* LDZ16 */
    MR, MR, MR, MR, CoissueFlag, 
    /* LDZ16STEP */
    MR, MR, MR, MR, MR, CoissueFlag, 
    /* LDZ16STEP_SI */
    MR, MR, MR, MR, imm8si, CoissueFlag, 
    /* LDZ16_ZI */
    MR, MR, MR, i32imm, CoissueFlag, 
    /* LDZ8 */
    MR, MR, MR, MR, CoissueFlag, 
    /* LDZ8STEP */
    MR, MR, MR, MR, MR, CoissueFlag, 
    /* LDZ8STEP_SI */
    MR, MR, MR, MR, imm8si, CoissueFlag, 
    /* LDZ8_ZI */
    MR, MR, MR, i32imm, CoissueFlag, 
    /* MAX */
    MR, MR, MR, CoissueFlag, 
    /* MAX_SI */
    MR, MR, imm16si, CoissueFlag, 
    /* MAX_ZI */
    MR, MR, imm16zi, CoissueFlag, 
    /* MIN */
    MR, MR, MR, CoissueFlag, 
    /* MIN_SI */
    MR, MR, imm16si, CoissueFlag, 
    /* MIN_ZI */
    MR, MR, imm16zi, CoissueFlag, 
    /* MOVZ */
    MR, MR, MR, MR, CoissueFlag, 
    /* MUL */
    MR, MR, MR, CoissueFlag, 
    /* MUL_SI */
    MR, MR, imm16si, CoissueFlag, 
    /* NOT */
    AR, AR, CoissueFlag, 
    /* NOT64 */
    ARPairOperand, ARPairOperand, CoissueFlag, 
    /* OR */
    MR, MR, MR, CoissueFlag, 
    /* OR64 */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* OR_A */
    AR, AR, AR, CoissueFlag, 
    /* OR_IZ */
    MR, MR, imm12iz, CoissueFlag, 
    /* OR_IZ_A */
    AR, AR, imm12iz, CoissueFlag, 
    /* OR_ZI */
    MR, MR, imm12zi, CoissueFlag, 
    /* OR_ZI_A */
    AR, AR, imm12zi, CoissueFlag, 
    /* POPC */
    MR, MR, CoissueFlag, 
    /* PUT */
    MR, imm8zi, CoissueFlag, 
    /* ROLL16 */
    MR, MR, MR, CoissueFlag, 
    /* ROLL16_A */
    AR, AR, AR, CoissueFlag, 
    /* ROLL32 */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* ROLL8L */
    MR, MR, MR, CoissueFlag, 
    /* ROLL8L_1 */
    AR, AR, AR, CoissueFlag, 
    /* ROLL8R */
    MR, MR, MR, CoissueFlag, 
    /* ROLL8R_1 */
    AR, AR, AR, CoissueFlag, 
    /* RPT */
    MR, Rel8Operand, CoissueFlag, 
    /* RPT_ZI */
    imm12zi, Rel8Operand, CoissueFlag, 
    /* RTN */
    MR, CoissueFlag, 
    /* RUN */
    MR, MR, RunOperand, CoissueFlag, 
    /* RUNALL */
    MR, MR, imm16zi, CoissueFlag, 
    /* SETZI */
    MR, Rel20Operand, CoissueFlag, 
    /* SETZI_A */
    AR, Rel20Operand, CoissueFlag, 
    /* SHL */
    MR, MR, MR, CoissueFlag, 
    /* SHL_ZI */
    MR, MR, imm12zi, CoissueFlag, 
    /* SHR */
    MR, MR, MR, CoissueFlag, 
    /* SHRS */
    MR, MR, MR, CoissueFlag, 
    /* SHRS_ZI */
    MR, MR, imm12zi, CoissueFlag, 
    /* SHR_ZI */
    MR, MR, imm12zi, CoissueFlag, 
    /* SHUF8X8HI */
    MR, MR, MR, CoissueFlag, 
    /* SHUF8X8HI_1 */
    AR, AR, AR, CoissueFlag, 
    /* SHUF8X8LO */
    MR, MR, MR, CoissueFlag, 
    /* SHUF8X8LO_1 */
    AR, AR, AR, CoissueFlag, 
    /* SORT4X16HI */
    MR, MR, MR, CoissueFlag, 
    /* SORT4X16HI_A */
    AR, AR, AR, CoissueFlag, 
    /* SORT4X16LO */
    MR, MR, MR, CoissueFlag, 
    /* SORT4X16LO_A */
    AR, AR, AR, CoissueFlag, 
    /* SORT4X16LO_BU */
    AR, BroadcastUpperOperand, AR, CoissueFlag, 
    /* SORT4X32HI */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* SORT4X32LO */
    ARPairOperand, ARPairOperand, ARPairOperand, CoissueFlag, 
    /* SORT8 */
    MR, MR, CoissueFlag, 
    /* SORT8X8HI */
    MR, MR, MR, CoissueFlag, 
    /* SORT8X8HI_1 */
    AR, AR, AR, CoissueFlag, 
    /* SORT8X8LO */
    MR, MR, MR, CoissueFlag, 
    /* SORT8X8LO_1 */
    AR, AR, AR, CoissueFlag, 
    /* SORT8_1 */
    AR, AR, CoissueFlag, 
    /* ST32STEP_A */
    MR, MR, MR, MR, AR, CoissueFlag, 
    /* ST32STEP_SI */
    MR, MR, MR, imm8si, MR, CoissueFlag, 
    /* ST32STEP_SI_A */
    MR, MR, MR, imm8si, AR, CoissueFlag, 
    /* ST32_A */
    AR, MR, MR, MR, CoissueFlag, 
    /* ST32_ZI */
    MR, MR, MR, i32imm, CoissueFlag, 
    /* ST32_ZI_A */
    AR, MR, MR, i32imm, CoissueFlag, 
    /* ST64PACE */
    MRPair, MR, MRPair, imm8zi, ARPairOperand, CoissueFlag, 
    /* ST64STEP_A */
    MR, MR, MR, MR, ARPairOperand, CoissueFlag, 
    /* ST64STEP_SI_A */
    MR, MR, MR, imm8si, ARPairOperand, CoissueFlag, 
    /* ST64_A */
    ARPairOperand, MR, MR, MR, CoissueFlag, 
    /* ST64_ZI_A */
    ARPairOperand, MR, MR, i32imm, CoissueFlag, 
    /* STM32 */
    MR, MR, MR, CoissueFlag, 
    /* STM32STEP */
    MR, MR, MR, MR, CoissueFlag, 
    /* SUB */
    MR, MR, MR, CoissueFlag, 
    /* SUB_SI */
    MR, MR, imm16si, CoissueFlag, 
    /* SUB_ZI */
    MR, MR, imm16zi, CoissueFlag, 
    /* SWAP8 */
    MR, MR, CoissueFlag, 
    /* SWAP8_1 */
    AR, AR, CoissueFlag, 
    /* TAPACK */
    MRPair, MR, MR, MR, CoissueFlag, 
    /* TRAP */
    imm4zi, CoissueFlag, 
    /* UGET */
    AR, imm8zi, CoissueFlag, 
    /* UPUT */
    AR, imm8zi, CoissueFlag, 
    /* URAND32 */
    AR, CoissueFlag, 
    /* URAND64 */
    ARPairOperand, CoissueFlag, 
    /* XNOR */
    MR, MR, MR, CoissueFlag, 
    /* XOR */
    MR, MR, MR, CoissueFlag, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace Colossus
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace Colossus {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace Colossus
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace Colossus {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace Colossus
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace Colossus {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace Colossus
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace Colossus_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace Colossus_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace Colossus_MC {

} // end namespace Colossus_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace Colossus_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_IsSupervisorBit = 3,
  Feature_IsWorkerBit = 4,
  Feature_IsIpu1And2Bit = 0,
  Feature_IsIpu2PlusBit = 1,
  Feature_IsIpu21PlusBit = 2,
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  if (FB[Colossus::ModeSupervisor])
    Features.set(Feature_IsSupervisorBit);
  if (!FB[Colossus::ModeSupervisor])
    Features.set(Feature_IsWorkerBit);
  if (FB[Colossus::ModeArchIpu1] || FB[Colossus::ModeArchIpu2] || FB[Colossus::ModeArchIpu21])
    Features.set(Feature_IsIpu1And2Bit);
  if (!FB[Colossus::ModeArchIpu1])
    Features.set(Feature_IsIpu2PlusBit);
  if (!FB[Colossus::ModeArchIpu1] && !FB[Colossus::ModeArchIpu2])
    Features.set(Feature_IsIpu21PlusBit);
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
    CEFBS_IsSupervisor,
    CEFBS_IsWorker,
    CEFBS_IsWorker_IsIpu1And2,
    CEFBS_IsWorker_IsIpu21Plus,
    CEFBS_IsWorker_IsIpu2Plus,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
    {Feature_IsSupervisorBit, },
    {Feature_IsWorkerBit, },
    {Feature_IsWorkerBit, Feature_IsIpu1And2Bit, },
    {Feature_IsWorkerBit, Feature_IsIpu21PlusBit, },
    {Feature_IsWorkerBit, Feature_IsIpu2PlusBit, },
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // INIT_UNDEF = 11
    CEFBS_None, // SUBREG_TO_REG = 12
    CEFBS_None, // COPY_TO_REGCLASS = 13
    CEFBS_None, // DBG_VALUE = 14
    CEFBS_None, // DBG_VALUE_LIST = 15
    CEFBS_None, // DBG_INSTR_REF = 16
    CEFBS_None, // DBG_PHI = 17
    CEFBS_None, // DBG_LABEL = 18
    CEFBS_None, // REG_SEQUENCE = 19
    CEFBS_None, // COPY = 20
    CEFBS_None, // BUNDLE = 21
    CEFBS_None, // LIFETIME_START = 22
    CEFBS_None, // LIFETIME_END = 23
    CEFBS_None, // PSEUDO_PROBE = 24
    CEFBS_None, // ARITH_FENCE = 25
    CEFBS_None, // STACKMAP = 26
    CEFBS_None, // FENTRY_CALL = 27
    CEFBS_None, // PATCHPOINT = 28
    CEFBS_None, // LOAD_STACK_GUARD = 29
    CEFBS_None, // PREALLOCATED_SETUP = 30
    CEFBS_None, // PREALLOCATED_ARG = 31
    CEFBS_None, // STATEPOINT = 32
    CEFBS_None, // LOCAL_ESCAPE = 33
    CEFBS_None, // FAULTING_OP = 34
    CEFBS_None, // PATCHABLE_OP = 35
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
    CEFBS_None, // PATCHABLE_RET = 37
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
    CEFBS_None, // PATCHABLE_TAIL_CALL = 39
    CEFBS_None, // PATCHABLE_EVENT_CALL = 40
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
    CEFBS_None, // FAKE_USE = 43
    CEFBS_None, // MEMBARRIER = 44
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
    CEFBS_None, // CONVERGENCECTRL_LOOP = 48
    CEFBS_None, // CONVERGENCECTRL_GLUE = 49
    CEFBS_None, // G_ASSERT_SEXT = 50
    CEFBS_None, // G_ASSERT_ZEXT = 51
    CEFBS_None, // G_ASSERT_ALIGN = 52
    CEFBS_None, // G_ADD = 53
    CEFBS_None, // G_SUB = 54
    CEFBS_None, // G_MUL = 55
    CEFBS_None, // G_SDIV = 56
    CEFBS_None, // G_UDIV = 57
    CEFBS_None, // G_SREM = 58
    CEFBS_None, // G_UREM = 59
    CEFBS_None, // G_SDIVREM = 60
    CEFBS_None, // G_UDIVREM = 61
    CEFBS_None, // G_AND = 62
    CEFBS_None, // G_OR = 63
    CEFBS_None, // G_XOR = 64
    CEFBS_None, // G_ABDS = 65
    CEFBS_None, // G_ABDU = 66
    CEFBS_None, // G_IMPLICIT_DEF = 67
    CEFBS_None, // G_PHI = 68
    CEFBS_None, // G_FRAME_INDEX = 69
    CEFBS_None, // G_GLOBAL_VALUE = 70
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
    CEFBS_None, // G_CONSTANT_POOL = 72
    CEFBS_None, // G_EXTRACT = 73
    CEFBS_None, // G_UNMERGE_VALUES = 74
    CEFBS_None, // G_INSERT = 75
    CEFBS_None, // G_MERGE_VALUES = 76
    CEFBS_None, // G_BUILD_VECTOR = 77
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
    CEFBS_None, // G_CONCAT_VECTORS = 79
    CEFBS_None, // G_PTRTOINT = 80
    CEFBS_None, // G_INTTOPTR = 81
    CEFBS_None, // G_BITCAST = 82
    CEFBS_None, // G_FREEZE = 83
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
    CEFBS_None, // G_INTRINSIC_TRUNC = 86
    CEFBS_None, // G_INTRINSIC_ROUND = 87
    CEFBS_None, // G_INTRINSIC_LRINT = 88
    CEFBS_None, // G_INTRINSIC_LLRINT = 89
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
    CEFBS_None, // G_READCYCLECOUNTER = 91
    CEFBS_None, // G_READSTEADYCOUNTER = 92
    CEFBS_None, // G_LOAD = 93
    CEFBS_None, // G_SEXTLOAD = 94
    CEFBS_None, // G_ZEXTLOAD = 95
    CEFBS_None, // G_INDEXED_LOAD = 96
    CEFBS_None, // G_INDEXED_SEXTLOAD = 97
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
    CEFBS_None, // G_STORE = 99
    CEFBS_None, // G_INDEXED_STORE = 100
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
    CEFBS_None, // G_ATOMIC_CMPXCHG = 102
    CEFBS_None, // G_ATOMICRMW_XCHG = 103
    CEFBS_None, // G_ATOMICRMW_ADD = 104
    CEFBS_None, // G_ATOMICRMW_SUB = 105
    CEFBS_None, // G_ATOMICRMW_AND = 106
    CEFBS_None, // G_ATOMICRMW_NAND = 107
    CEFBS_None, // G_ATOMICRMW_OR = 108
    CEFBS_None, // G_ATOMICRMW_XOR = 109
    CEFBS_None, // G_ATOMICRMW_MAX = 110
    CEFBS_None, // G_ATOMICRMW_MIN = 111
    CEFBS_None, // G_ATOMICRMW_UMAX = 112
    CEFBS_None, // G_ATOMICRMW_UMIN = 113
    CEFBS_None, // G_ATOMICRMW_FADD = 114
    CEFBS_None, // G_ATOMICRMW_FSUB = 115
    CEFBS_None, // G_ATOMICRMW_FMAX = 116
    CEFBS_None, // G_ATOMICRMW_FMIN = 117
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 118
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 119
    CEFBS_None, // G_ATOMICRMW_USUB_COND = 120
    CEFBS_None, // G_ATOMICRMW_USUB_SAT = 121
    CEFBS_None, // G_FENCE = 122
    CEFBS_None, // G_PREFETCH = 123
    CEFBS_None, // G_BRCOND = 124
    CEFBS_None, // G_BRINDIRECT = 125
    CEFBS_None, // G_INVOKE_REGION_START = 126
    CEFBS_None, // G_INTRINSIC = 127
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 128
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 129
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 130
    CEFBS_None, // G_ANYEXT = 131
    CEFBS_None, // G_TRUNC = 132
    CEFBS_None, // G_CONSTANT = 133
    CEFBS_None, // G_FCONSTANT = 134
    CEFBS_None, // G_VASTART = 135
    CEFBS_None, // G_VAARG = 136
    CEFBS_None, // G_SEXT = 137
    CEFBS_None, // G_SEXT_INREG = 138
    CEFBS_None, // G_ZEXT = 139
    CEFBS_None, // G_SHL = 140
    CEFBS_None, // G_LSHR = 141
    CEFBS_None, // G_ASHR = 142
    CEFBS_None, // G_FSHL = 143
    CEFBS_None, // G_FSHR = 144
    CEFBS_None, // G_ROTR = 145
    CEFBS_None, // G_ROTL = 146
    CEFBS_None, // G_ICMP = 147
    CEFBS_None, // G_FCMP = 148
    CEFBS_None, // G_SCMP = 149
    CEFBS_None, // G_UCMP = 150
    CEFBS_None, // G_SELECT = 151
    CEFBS_None, // G_UADDO = 152
    CEFBS_None, // G_UADDE = 153
    CEFBS_None, // G_USUBO = 154
    CEFBS_None, // G_USUBE = 155
    CEFBS_None, // G_SADDO = 156
    CEFBS_None, // G_SADDE = 157
    CEFBS_None, // G_SSUBO = 158
    CEFBS_None, // G_SSUBE = 159
    CEFBS_None, // G_UMULO = 160
    CEFBS_None, // G_SMULO = 161
    CEFBS_None, // G_UMULH = 162
    CEFBS_None, // G_SMULH = 163
    CEFBS_None, // G_UADDSAT = 164
    CEFBS_None, // G_SADDSAT = 165
    CEFBS_None, // G_USUBSAT = 166
    CEFBS_None, // G_SSUBSAT = 167
    CEFBS_None, // G_USHLSAT = 168
    CEFBS_None, // G_SSHLSAT = 169
    CEFBS_None, // G_SMULFIX = 170
    CEFBS_None, // G_UMULFIX = 171
    CEFBS_None, // G_SMULFIXSAT = 172
    CEFBS_None, // G_UMULFIXSAT = 173
    CEFBS_None, // G_SDIVFIX = 174
    CEFBS_None, // G_UDIVFIX = 175
    CEFBS_None, // G_SDIVFIXSAT = 176
    CEFBS_None, // G_UDIVFIXSAT = 177
    CEFBS_None, // G_FADD = 178
    CEFBS_None, // G_FSUB = 179
    CEFBS_None, // G_FMUL = 180
    CEFBS_None, // G_FMA = 181
    CEFBS_None, // G_FMAD = 182
    CEFBS_None, // G_FDIV = 183
    CEFBS_None, // G_FREM = 184
    CEFBS_None, // G_FPOW = 185
    CEFBS_None, // G_FPOWI = 186
    CEFBS_None, // G_FEXP = 187
    CEFBS_None, // G_FEXP2 = 188
    CEFBS_None, // G_FEXP10 = 189
    CEFBS_None, // G_FLOG = 190
    CEFBS_None, // G_FLOG2 = 191
    CEFBS_None, // G_FLOG10 = 192
    CEFBS_None, // G_FLDEXP = 193
    CEFBS_None, // G_FFREXP = 194
    CEFBS_None, // G_FNEG = 195
    CEFBS_None, // G_FPEXT = 196
    CEFBS_None, // G_FPTRUNC = 197
    CEFBS_None, // G_FPTOSI = 198
    CEFBS_None, // G_FPTOUI = 199
    CEFBS_None, // G_SITOFP = 200
    CEFBS_None, // G_UITOFP = 201
    CEFBS_None, // G_FPTOSI_SAT = 202
    CEFBS_None, // G_FPTOUI_SAT = 203
    CEFBS_None, // G_FABS = 204
    CEFBS_None, // G_FCOPYSIGN = 205
    CEFBS_None, // G_IS_FPCLASS = 206
    CEFBS_None, // G_FCANONICALIZE = 207
    CEFBS_None, // G_FMINNUM = 208
    CEFBS_None, // G_FMAXNUM = 209
    CEFBS_None, // G_FMINNUM_IEEE = 210
    CEFBS_None, // G_FMAXNUM_IEEE = 211
    CEFBS_None, // G_FMINIMUM = 212
    CEFBS_None, // G_FMAXIMUM = 213
    CEFBS_None, // G_GET_FPENV = 214
    CEFBS_None, // G_SET_FPENV = 215
    CEFBS_None, // G_RESET_FPENV = 216
    CEFBS_None, // G_GET_FPMODE = 217
    CEFBS_None, // G_SET_FPMODE = 218
    CEFBS_None, // G_RESET_FPMODE = 219
    CEFBS_None, // G_PTR_ADD = 220
    CEFBS_None, // G_PTRMASK = 221
    CEFBS_None, // G_SMIN = 222
    CEFBS_None, // G_SMAX = 223
    CEFBS_None, // G_UMIN = 224
    CEFBS_None, // G_UMAX = 225
    CEFBS_None, // G_ABS = 226
    CEFBS_None, // G_LROUND = 227
    CEFBS_None, // G_LLROUND = 228
    CEFBS_None, // G_BR = 229
    CEFBS_None, // G_BRJT = 230
    CEFBS_None, // G_VSCALE = 231
    CEFBS_None, // G_INSERT_SUBVECTOR = 232
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 233
    CEFBS_None, // G_INSERT_VECTOR_ELT = 234
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 235
    CEFBS_None, // G_SHUFFLE_VECTOR = 236
    CEFBS_None, // G_SPLAT_VECTOR = 237
    CEFBS_None, // G_STEP_VECTOR = 238
    CEFBS_None, // G_VECTOR_COMPRESS = 239
    CEFBS_None, // G_CTTZ = 240
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 241
    CEFBS_None, // G_CTLZ = 242
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 243
    CEFBS_None, // G_CTPOP = 244
    CEFBS_None, // G_BSWAP = 245
    CEFBS_None, // G_BITREVERSE = 246
    CEFBS_None, // G_FCEIL = 247
    CEFBS_None, // G_FCOS = 248
    CEFBS_None, // G_FSIN = 249
    CEFBS_None, // G_FSINCOS = 250
    CEFBS_None, // G_FTAN = 251
    CEFBS_None, // G_FACOS = 252
    CEFBS_None, // G_FASIN = 253
    CEFBS_None, // G_FATAN = 254
    CEFBS_None, // G_FATAN2 = 255
    CEFBS_None, // G_FCOSH = 256
    CEFBS_None, // G_FSINH = 257
    CEFBS_None, // G_FTANH = 258
    CEFBS_None, // G_FSQRT = 259
    CEFBS_None, // G_FFLOOR = 260
    CEFBS_None, // G_FRINT = 261
    CEFBS_None, // G_FNEARBYINT = 262
    CEFBS_None, // G_ADDRSPACE_CAST = 263
    CEFBS_None, // G_BLOCK_ADDR = 264
    CEFBS_None, // G_JUMP_TABLE = 265
    CEFBS_None, // G_DYN_STACKALLOC = 266
    CEFBS_None, // G_STACKSAVE = 267
    CEFBS_None, // G_STACKRESTORE = 268
    CEFBS_None, // G_STRICT_FADD = 269
    CEFBS_None, // G_STRICT_FSUB = 270
    CEFBS_None, // G_STRICT_FMUL = 271
    CEFBS_None, // G_STRICT_FDIV = 272
    CEFBS_None, // G_STRICT_FREM = 273
    CEFBS_None, // G_STRICT_FMA = 274
    CEFBS_None, // G_STRICT_FSQRT = 275
    CEFBS_None, // G_STRICT_FLDEXP = 276
    CEFBS_None, // G_READ_REGISTER = 277
    CEFBS_None, // G_WRITE_REGISTER = 278
    CEFBS_None, // G_MEMCPY = 279
    CEFBS_None, // G_MEMCPY_INLINE = 280
    CEFBS_None, // G_MEMMOVE = 281
    CEFBS_None, // G_MEMSET = 282
    CEFBS_None, // G_BZERO = 283
    CEFBS_None, // G_TRAP = 284
    CEFBS_None, // G_DEBUGTRAP = 285
    CEFBS_None, // G_UBSANTRAP = 286
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 287
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 288
    CEFBS_None, // G_VECREDUCE_FADD = 289
    CEFBS_None, // G_VECREDUCE_FMUL = 290
    CEFBS_None, // G_VECREDUCE_FMAX = 291
    CEFBS_None, // G_VECREDUCE_FMIN = 292
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 293
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 294
    CEFBS_None, // G_VECREDUCE_ADD = 295
    CEFBS_None, // G_VECREDUCE_MUL = 296
    CEFBS_None, // G_VECREDUCE_AND = 297
    CEFBS_None, // G_VECREDUCE_OR = 298
    CEFBS_None, // G_VECREDUCE_XOR = 299
    CEFBS_None, // G_VECREDUCE_SMAX = 300
    CEFBS_None, // G_VECREDUCE_SMIN = 301
    CEFBS_None, // G_VECREDUCE_UMAX = 302
    CEFBS_None, // G_VECREDUCE_UMIN = 303
    CEFBS_None, // G_SBFX = 304
    CEFBS_None, // G_UBFX = 305
    CEFBS_None, // ADJCALLSTACKDOWN = 306
    CEFBS_None, // ADJCALLSTACKUP = 307
    CEFBS_None, // CALLIND = 308
    CEFBS_None, // CALL_PSEUDO = 309
    CEFBS_None, // CLOOP_BEGIN_TERMINATOR = 310
    CEFBS_None, // CLOOP_BEGIN_VALUE = 311
    CEFBS_None, // CLOOP_END_BRANCH = 312
    CEFBS_None, // CLOOP_END_VALUE = 313
    CEFBS_None, // CLOOP_GUARD_BRANCH = 314
    CEFBS_None, // FRAME_INDEX = 315
    CEFBS_None, // FRAME_TO_ARGS_OFFSET = 316
    CEFBS_None, // ICALL = 317
    CEFBS_None, // LABEL = 318
    CEFBS_None, // LD32_ACC_FI = 319
    CEFBS_None, // LD32_A_FI = 320
    CEFBS_None, // LD32_FI = 321
    CEFBS_None, // LD64_ACC_FI = 322
    CEFBS_None, // LD64_A_FI = 323
    CEFBS_None, // LD64_FI = 324
    CEFBS_None, // LDCONST = 325
    CEFBS_None, // LDCONST_A = 326
    CEFBS_None, // LDS16_FI = 327
    CEFBS_None, // LDS8_FI = 328
    CEFBS_None, // LDZ16_A_FI = 329
    CEFBS_None, // LDZ16_FI = 330
    CEFBS_None, // LDZ8_FI = 331
    CEFBS_None, // MEM_BARRIER = 332
    CEFBS_None, // RTN_PSEUDO = 333
    CEFBS_None, // RTN_REG_HOLDER = 334
    CEFBS_None, // SELECT_F16 = 335
    CEFBS_None, // SELECT_F32 = 336
    CEFBS_None, // SELECT_V2F16 = 337
    CEFBS_None, // SELECT_V2F32 = 338
    CEFBS_None, // SELECT_V4F16 = 339
    CEFBS_None, // SETLR = 340
    CEFBS_None, // ST32_ACC_FI = 341
    CEFBS_None, // ST32_A_FI = 342
    CEFBS_None, // ST32_FI = 343
    CEFBS_None, // ST64_ACC_FI = 344
    CEFBS_None, // ST64_A_FI = 345
    CEFBS_None, // ST64_FI = 346
    CEFBS_None, // STACKRESTORE = 347
    CEFBS_None, // STACKSAVE = 348
    CEFBS_None, // SUB_IMM = 349
    CEFBS_None, // ABS = 350
    CEFBS_None, // ADD = 351
    CEFBS_None, // ADD_SI = 352
    CEFBS_None, // ADD_ZI = 353
    CEFBS_None, // AND = 354
    CEFBS_IsWorker, // AND64 = 355
    CEFBS_None, // ANDC = 356
    CEFBS_IsWorker, // ANDC64 = 357
    CEFBS_IsWorker, // ANDC_A = 358
    CEFBS_IsWorker, // ANDC_IZ_A = 359
    CEFBS_None, // ANDC_ZI = 360
    CEFBS_IsWorker, // ANDC_ZI_A = 361
    CEFBS_IsWorker, // AND_A = 362
    CEFBS_IsWorker, // AND_IZ_A = 363
    CEFBS_None, // AND_ZI = 364
    CEFBS_IsWorker, // AND_ZI_A = 365
    CEFBS_IsWorker, // ATOM = 366
    CEFBS_None, // BITREV8 = 367
    CEFBS_None, // BR = 368
    CEFBS_None, // BRIND = 369
    CEFBS_None, // BRNEG = 370
    CEFBS_None, // BRNZ = 371
    CEFBS_None, // BRNZDEC = 372
    CEFBS_None, // BRPOS = 373
    CEFBS_None, // BRZ = 374
    CEFBS_None, // CALL = 375
    CEFBS_None, // CLZ = 376
    CEFBS_None, // CMPEQ = 377
    CEFBS_None, // CMPEQ_SI = 378
    CEFBS_None, // CMPEQ_ZI = 379
    CEFBS_None, // CMPNE = 380
    CEFBS_None, // CMPSLT = 381
    CEFBS_None, // CMPSLT_SI = 382
    CEFBS_None, // CMPULT = 383
    CEFBS_None, // CMPULT_ZI = 384
    CEFBS_None, // CMS = 385
    CEFBS_IsWorker_IsIpu1And2, // EXITNEG = 386
    CEFBS_IsWorker_IsIpu1And2, // EXITNZ = 387
    CEFBS_IsWorker_IsIpu1And2, // EXITPOS = 388
    CEFBS_IsWorker_IsIpu1And2, // EXITZ = 389
    CEFBS_IsWorker, // F16TOF32 = 390
    CEFBS_IsWorker, // F16V2ABSADD = 391
    CEFBS_IsWorker, // F16V2ABSMAX = 392
    CEFBS_IsWorker, // F16V2ADD = 393
    CEFBS_IsWorker, // F16V2ADD_BL = 394
    CEFBS_IsWorker, // F16V2ADD_BU = 395
    CEFBS_IsWorker, // F16V2CLAMP = 396
    CEFBS_IsWorker, // F16V2CLASS = 397
    CEFBS_IsWorker, // F16V2CMAC = 398
    CEFBS_IsWorker, // F16V2CMPEQ = 399
    CEFBS_IsWorker, // F16V2CMPEQ_BL = 400
    CEFBS_IsWorker, // F16V2CMPEQ_BU = 401
    CEFBS_IsWorker, // F16V2CMPGE = 402
    CEFBS_IsWorker, // F16V2CMPGE_BL = 403
    CEFBS_IsWorker, // F16V2CMPGE_BU = 404
    CEFBS_IsWorker, // F16V2CMPGT = 405
    CEFBS_IsWorker, // F16V2CMPGT_BL = 406
    CEFBS_IsWorker, // F16V2CMPGT_BU = 407
    CEFBS_IsWorker, // F16V2CMPLE = 408
    CEFBS_IsWorker, // F16V2CMPLE_BL = 409
    CEFBS_IsWorker, // F16V2CMPLE_BU = 410
    CEFBS_IsWorker, // F16V2CMPLT = 411
    CEFBS_IsWorker, // F16V2CMPLT_BL = 412
    CEFBS_IsWorker, // F16V2CMPLT_BU = 413
    CEFBS_IsWorker, // F16V2CMPNE = 414
    CEFBS_IsWorker, // F16V2CMPNE_BL = 415
    CEFBS_IsWorker, // F16V2CMPNE_BU = 416
    CEFBS_IsWorker, // F16V2EXP = 417
    CEFBS_IsWorker, // F16V2EXP2 = 418
    CEFBS_IsWorker, // F16V2GINA = 419
    CEFBS_IsWorker, // F16V2GRAND = 420
    CEFBS_IsWorker, // F16V2LN = 421
    CEFBS_IsWorker, // F16V2LOG2 = 422
    CEFBS_IsWorker, // F16V2MAX = 423
    CEFBS_IsWorker, // F16V2MAXC = 424
    CEFBS_IsWorker, // F16V2MIN = 425
    CEFBS_IsWorker, // F16V2MUL = 426
    CEFBS_IsWorker, // F16V2MUL_BL = 427
    CEFBS_IsWorker, // F16V2MUL_BU = 428
    CEFBS_IsWorker, // F16V2SIGMOID = 429
    CEFBS_IsWorker, // F16V2SUB = 430
    CEFBS_IsWorker, // F16V2SUB_BL = 431
    CEFBS_IsWorker, // F16V2SUB_BU = 432
    CEFBS_IsWorker, // F16V2SUFROMUI = 433
    CEFBS_IsWorker, // F16V2SUM = 434
    CEFBS_IsWorker, // F16V2TANH = 435
    CEFBS_IsWorker, // F16V2TOF32 = 436
    CEFBS_IsWorker_IsIpu21Plus, // F16V2TOF8 = 437
    CEFBS_IsWorker, // F16V4ABSACC = 438
    CEFBS_IsWorker, // F16V4ABSADD = 439
    CEFBS_IsWorker, // F16V4ABSMAX = 440
    CEFBS_IsWorker, // F16V4ACC = 441
    CEFBS_IsWorker, // F16V4ADD = 442
    CEFBS_IsWorker, // F16V4ADD_BL = 443
    CEFBS_IsWorker, // F16V4ADD_BU = 444
    CEFBS_IsWorker, // F16V4CLAMP = 445
    CEFBS_IsWorker, // F16V4CLASS = 446
    CEFBS_IsWorker, // F16V4CMAC = 447
    CEFBS_IsWorker, // F16V4CMPEQ = 448
    CEFBS_IsWorker, // F16V4CMPEQ_BL = 449
    CEFBS_IsWorker, // F16V4CMPEQ_BU = 450
    CEFBS_IsWorker, // F16V4CMPGE = 451
    CEFBS_IsWorker, // F16V4CMPGE_BL = 452
    CEFBS_IsWorker, // F16V4CMPGE_BU = 453
    CEFBS_IsWorker, // F16V4CMPGT = 454
    CEFBS_IsWorker, // F16V4CMPGT_BL = 455
    CEFBS_IsWorker, // F16V4CMPGT_BU = 456
    CEFBS_IsWorker, // F16V4CMPLE = 457
    CEFBS_IsWorker, // F16V4CMPLE_BL = 458
    CEFBS_IsWorker, // F16V4CMPLE_BU = 459
    CEFBS_IsWorker, // F16V4CMPLT = 460
    CEFBS_IsWorker, // F16V4CMPLT_BL = 461
    CEFBS_IsWorker, // F16V4CMPLT_BU = 462
    CEFBS_IsWorker, // F16V4CMPNE = 463
    CEFBS_IsWorker, // F16V4CMPNE_BL = 464
    CEFBS_IsWorker, // F16V4CMPNE_BU = 465
    CEFBS_IsWorker, // F16V4GACC = 466
    CEFBS_IsWorker, // F16V4HIHOAMP = 467
    CEFBS_IsWorker, // F16V4HIHOSLIC = 468
    CEFBS_IsWorker_IsIpu2Plus, // F16V4HIHOV4AMP = 469
    CEFBS_IsWorker_IsIpu2Plus, // F16V4HIHOV4SLIC = 470
    CEFBS_IsWorker, // F16V4ISTACC = 471
    CEFBS_IsWorker, // F16V4MAX = 472
    CEFBS_IsWorker, // F16V4MAXC = 473
    CEFBS_IsWorker, // F16V4MIN = 474
    CEFBS_IsWorker, // F16V4MIX = 475
    CEFBS_IsWorker, // F16V4MUL = 476
    CEFBS_IsWorker, // F16V4MUL_BL = 477
    CEFBS_IsWorker, // F16V4MUL_BU = 478
    CEFBS_IsWorker, // F16V4RMASK = 479
    CEFBS_IsWorker, // F16V4SIHOAMP = 480
    CEFBS_IsWorker, // F16V4SIHOSLIC = 481
    CEFBS_IsWorker, // F16V4SISOAMP = 482
    CEFBS_IsWorker, // F16V4SISOSLIC = 483
    CEFBS_IsWorker, // F16V4STACC = 484
    CEFBS_IsWorker, // F16V4SUB = 485
    CEFBS_IsWorker, // F16V4SUB_BL = 486
    CEFBS_IsWorker, // F16V4SUB_BU = 487
    CEFBS_IsWorker, // F16V4SUFROMUI = 488
    CEFBS_IsWorker, // F16V4SUM = 489
    CEFBS_IsWorker, // F16V8ABSACC = 490
    CEFBS_IsWorker, // F16V8ACC = 491
    CEFBS_IsWorker, // F16V8SQACC = 492
    CEFBS_IsWorker_IsIpu21Plus, // F16V8TOF8 = 493
    CEFBS_IsWorker, // F32ABSADD = 494
    CEFBS_IsWorker, // F32ABSMAX = 495
    CEFBS_IsWorker, // F32ADD = 496
    CEFBS_IsWorker, // F32CLAMP = 497
    CEFBS_IsWorker, // F32CLASS = 498
    CEFBS_IsWorker, // F32CMPEQ = 499
    CEFBS_IsWorker, // F32CMPGE = 500
    CEFBS_IsWorker, // F32CMPGT = 501
    CEFBS_IsWorker, // F32CMPLE = 502
    CEFBS_IsWorker, // F32CMPLT = 503
    CEFBS_IsWorker, // F32CMPNE = 504
    CEFBS_IsWorker, // F32DIV = 505
    CEFBS_IsWorker, // F32EXP = 506
    CEFBS_IsWorker, // F32EXP2 = 507
    CEFBS_IsWorker, // F32FROMI32 = 508
    CEFBS_IsWorker, // F32FROMUI32 = 509
    CEFBS_IsWorker, // F32INT = 510
    CEFBS_IsWorker, // F32LN = 511
    CEFBS_IsWorker, // F32LOG2 = 512
    CEFBS_IsWorker, // F32MAC = 513
    CEFBS_IsWorker, // F32MAX = 514
    CEFBS_IsWorker, // F32MIN = 515
    CEFBS_IsWorker, // F32MUL = 516
    CEFBS_IsWorker, // F32OORX = 517
    CEFBS_IsWorker, // F32OOX = 518
    CEFBS_IsWorker, // F32SIGMOID = 519
    CEFBS_IsWorker, // F32SISOAMP = 520
    CEFBS_IsWorker, // F32SISOSLIC = 521
    CEFBS_IsWorker_IsIpu2Plus, // F32SISOV2AMP = 522
    CEFBS_IsWorker, // F32SQRT = 523
    CEFBS_IsWorker, // F32SUB = 524
    CEFBS_IsWorker, // F32SUFROMUI = 525
    CEFBS_IsWorker, // F32TANH = 526
    CEFBS_IsWorker, // F32TOF16 = 527
    CEFBS_IsWorker, // F32TOI32 = 528
    CEFBS_IsWorker, // F32TOUI32 = 529
    CEFBS_IsWorker, // F32V2ABSADD = 530
    CEFBS_IsWorker, // F32V2ABSMAX = 531
    CEFBS_IsWorker, // F32V2ADD = 532
    CEFBS_IsWorker, // F32V2ADD_BL = 533
    CEFBS_IsWorker, // F32V2AOP = 534
    CEFBS_IsWorker, // F32V2AXPY = 535
    CEFBS_IsWorker, // F32V2CLAMP = 536
    CEFBS_IsWorker, // F32V2CLASS = 537
    CEFBS_IsWorker, // F32V2CMPEQ = 538
    CEFBS_IsWorker, // F32V2CMPEQ_BL = 539
    CEFBS_IsWorker, // F32V2CMPGE = 540
    CEFBS_IsWorker, // F32V2CMPGE_BL = 541
    CEFBS_IsWorker, // F32V2CMPGT = 542
    CEFBS_IsWorker, // F32V2CMPGT_BL = 543
    CEFBS_IsWorker, // F32V2CMPLE = 544
    CEFBS_IsWorker, // F32V2CMPLE_BL = 545
    CEFBS_IsWorker, // F32V2CMPLT = 546
    CEFBS_IsWorker, // F32V2CMPLT_BL = 547
    CEFBS_IsWorker, // F32V2CMPNE = 548
    CEFBS_IsWorker, // F32V2CMPNE_BL = 549
    CEFBS_IsWorker, // F32V2GINA = 550
    CEFBS_IsWorker, // F32V2GRAND = 551
    CEFBS_IsWorker, // F32V2MAC = 552
    CEFBS_IsWorker, // F32V2MAX = 553
    CEFBS_IsWorker, // F32V2MIN = 554
    CEFBS_IsWorker, // F32V2MUL = 555
    CEFBS_IsWorker, // F32V2MUL_BL = 556
    CEFBS_IsWorker, // F32V2RMASK = 557
    CEFBS_IsWorker, // F32V2SUB = 558
    CEFBS_IsWorker, // F32V2SUB_BL = 559
    CEFBS_IsWorker, // F32V2SUFROMUI = 560
    CEFBS_IsWorker, // F32V2TOF16 = 561
    CEFBS_IsWorker, // F32V4ABSACC = 562
    CEFBS_IsWorker, // F32V4ACC = 563
    CEFBS_IsWorker, // F32V4SQACC = 564
    CEFBS_IsWorker, // F32V4TOF16 = 565
    CEFBS_IsWorker_IsIpu21Plus, // F8V2TOF16 = 566
    CEFBS_IsWorker_IsIpu21Plus, // F8V4CLASS = 567
    CEFBS_IsWorker_IsIpu21Plus, // F8V4TOF16 = 568
    CEFBS_IsWorker_IsIpu21Plus, // F8V8HIHOV4AMP = 569
    CEFBS_IsWorker_IsIpu21Plus, // F8V8HIHOV4SLIC = 570
    CEFBS_None, // GET = 571
    CEFBS_IsWorker, // LD128 = 572
    CEFBS_IsSupervisor, // LD128PUTCS = 573
    CEFBS_IsWorker, // LD128STEP = 574
    CEFBS_IsWorker, // LD128STEP_SI = 575
    CEFBS_IsWorker, // LD128_ZI = 576
    CEFBS_IsWorker, // LD2X64PACE = 577
    CEFBS_IsWorker, // LD2XST64PACE = 578
    CEFBS_None, // LD32 = 579
    CEFBS_None, // LD32STEP = 580
    CEFBS_IsWorker, // LD32STEP_A = 581
    CEFBS_None, // LD32STEP_SI = 582
    CEFBS_IsWorker, // LD32STEP_SI_A = 583
    CEFBS_IsWorker, // LD32_A = 584
    CEFBS_None, // LD32_ZI = 585
    CEFBS_IsWorker, // LD32_ZI_A = 586
    CEFBS_IsWorker, // LD64A32 = 587
    CEFBS_IsWorker, // LD64A32PACE = 588
    CEFBS_IsWorker, // LD64B16PACE = 589
    CEFBS_IsSupervisor, // LD64PUTCS = 590
    CEFBS_IsWorker, // LD64STEP_A = 591
    CEFBS_IsWorker, // LD64STEP_SI_A = 592
    CEFBS_IsWorker, // LD64_A = 593
    CEFBS_IsWorker, // LD64_ZI_A = 594
    CEFBS_IsWorker, // LDB16 = 595
    CEFBS_IsWorker, // LDB16B16 = 596
    CEFBS_IsWorker, // LDB16STEP = 597
    CEFBS_IsWorker, // LDB16STEP_SI = 598
    CEFBS_IsWorker, // LDB16_ZI = 599
    CEFBS_IsWorker_IsIpu21Plus, // LDB8 = 600
    CEFBS_IsWorker_IsIpu21Plus, // LDB8_ZI = 601
    CEFBS_IsWorker, // LDD16A32 = 602
    CEFBS_IsWorker, // LDD16A64 = 603
    CEFBS_IsWorker, // LDD16B16 = 604
    CEFBS_IsWorker, // LDD16V2A32 = 605
    CEFBS_None, // LDS16 = 606
    CEFBS_None, // LDS16STEP = 607
    CEFBS_None, // LDS16STEP_SI = 608
    CEFBS_None, // LDS16_ZI = 609
    CEFBS_None, // LDS8 = 610
    CEFBS_None, // LDS8STEP = 611
    CEFBS_None, // LDS8STEP_SI = 612
    CEFBS_None, // LDS8_ZI = 613
    CEFBS_IsWorker, // LDST64PACE = 614
    CEFBS_None, // LDZ16 = 615
    CEFBS_None, // LDZ16STEP = 616
    CEFBS_None, // LDZ16STEP_SI = 617
    CEFBS_None, // LDZ16_ZI = 618
    CEFBS_None, // LDZ8 = 619
    CEFBS_None, // LDZ8STEP = 620
    CEFBS_None, // LDZ8STEP_SI = 621
    CEFBS_None, // LDZ8_ZI = 622
    CEFBS_None, // MAX = 623
    CEFBS_None, // MAX_SI = 624
    CEFBS_None, // MAX_ZI = 625
    CEFBS_None, // MIN = 626
    CEFBS_None, // MIN_SI = 627
    CEFBS_None, // MIN_ZI = 628
    CEFBS_None, // MOVZ = 629
    CEFBS_None, // MUL = 630
    CEFBS_None, // MUL_SI = 631
    CEFBS_IsWorker, // NOT = 632
    CEFBS_IsWorker, // NOT64 = 633
    CEFBS_None, // OR = 634
    CEFBS_IsWorker, // OR64 = 635
    CEFBS_IsWorker, // OR_A = 636
    CEFBS_None, // OR_IZ = 637
    CEFBS_IsWorker, // OR_IZ_A = 638
    CEFBS_None, // OR_ZI = 639
    CEFBS_IsWorker, // OR_ZI_A = 640
    CEFBS_None, // POPC = 641
    CEFBS_None, // PUT = 642
    CEFBS_None, // ROLL16 = 643
    CEFBS_IsWorker, // ROLL16_A = 644
    CEFBS_IsWorker, // ROLL32 = 645
    CEFBS_None, // ROLL8L = 646
    CEFBS_IsWorker_IsIpu21Plus, // ROLL8L_1 = 647
    CEFBS_None, // ROLL8R = 648
    CEFBS_IsWorker_IsIpu21Plus, // ROLL8R_1 = 649
    CEFBS_IsWorker, // RPT = 650
    CEFBS_IsWorker, // RPT_ZI = 651
    CEFBS_None, // RTN = 652
    CEFBS_IsSupervisor, // RUN = 653
    CEFBS_IsSupervisor, // RUNALL = 654
    CEFBS_None, // SETZI = 655
    CEFBS_IsWorker, // SETZI_A = 656
    CEFBS_None, // SHL = 657
    CEFBS_None, // SHL_ZI = 658
    CEFBS_None, // SHR = 659
    CEFBS_None, // SHRS = 660
    CEFBS_None, // SHRS_ZI = 661
    CEFBS_None, // SHR_ZI = 662
    CEFBS_None, // SHUF8X8HI = 663
    CEFBS_IsWorker_IsIpu21Plus, // SHUF8X8HI_1 = 664
    CEFBS_None, // SHUF8X8LO = 665
    CEFBS_IsWorker_IsIpu21Plus, // SHUF8X8LO_1 = 666
    CEFBS_None, // SORT4X16HI = 667
    CEFBS_IsWorker, // SORT4X16HI_A = 668
    CEFBS_None, // SORT4X16LO = 669
    CEFBS_IsWorker, // SORT4X16LO_A = 670
    CEFBS_IsWorker, // SORT4X16LO_BU = 671
    CEFBS_IsWorker, // SORT4X32HI = 672
    CEFBS_IsWorker, // SORT4X32LO = 673
    CEFBS_None, // SORT8 = 674
    CEFBS_None, // SORT8X8HI = 675
    CEFBS_IsWorker_IsIpu21Plus, // SORT8X8HI_1 = 676
    CEFBS_None, // SORT8X8LO = 677
    CEFBS_IsWorker_IsIpu21Plus, // SORT8X8LO_1 = 678
    CEFBS_IsWorker_IsIpu21Plus, // SORT8_1 = 679
    CEFBS_IsWorker, // ST32STEP_A = 680
    CEFBS_None, // ST32STEP_SI = 681
    CEFBS_IsWorker, // ST32STEP_SI_A = 682
    CEFBS_IsWorker, // ST32_A = 683
    CEFBS_None, // ST32_ZI = 684
    CEFBS_IsWorker, // ST32_ZI_A = 685
    CEFBS_IsWorker, // ST64PACE = 686
    CEFBS_IsWorker, // ST64STEP_A = 687
    CEFBS_IsWorker, // ST64STEP_SI_A = 688
    CEFBS_IsWorker, // ST64_A = 689
    CEFBS_IsWorker, // ST64_ZI_A = 690
    CEFBS_None, // STM32 = 691
    CEFBS_None, // STM32STEP = 692
    CEFBS_None, // SUB = 693
    CEFBS_None, // SUB_SI = 694
    CEFBS_None, // SUB_ZI = 695
    CEFBS_None, // SWAP8 = 696
    CEFBS_IsWorker_IsIpu21Plus, // SWAP8_1 = 697
    CEFBS_IsWorker, // TAPACK = 698
    CEFBS_None, // TRAP = 699
    CEFBS_IsWorker, // UGET = 700
    CEFBS_IsWorker, // UPUT = 701
    CEFBS_IsWorker, // URAND32 = 702
    CEFBS_IsWorker, // URAND64 = 703
    CEFBS_None, // XNOR = 704
    CEFBS_None, // XOR = 705
  };

  assert(Opcode < 706);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace Colossus_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace Colossus_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace Colossus_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace Colossus_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  "Feature_IsIpu1And2",
  "Feature_IsIpu2Plus",
  "Feature_IsIpu21Plus",
  "Feature_IsSupervisor",
  "Feature_IsWorker",
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &ColossusInstrNameData[ColossusInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace Colossus_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER

