/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t ColossusMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const {
  static const uint64_t InstBits[] = {
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(1107324928),	// ABS
    UINT64_C(1140850689),	// ADD
    UINT64_C(570425344),	// ADD_SI
    UINT64_C(536870912),	// ADD_ZI
    UINT64_C(1140850691),	// AND
    UINT64_C(1476396546),	// AND64
    UINT64_C(1140850944),	// ANDC
    UINT64_C(1476396547),	// ANDC64
    UINT64_C(1476396545),	// ANDC_A
    UINT64_C(1375793152),	// ANDC_IZ_A
    UINT64_C(1107341312),	// ANDC_ZI
    UINT64_C(1375776768),	// ANDC_ZI_A
    UINT64_C(1476396544),	// AND_A
    UINT64_C(1375780864),	// AND_IZ_A
    UINT64_C(1107329024),	// AND_ZI
    UINT64_C(1375764480),	// AND_ZI_A
    UINT64_C(1560281088),	// ATOM
    UINT64_C(1107296256),	// BITREV8
    UINT64_C(1082130432),	// BR
    UINT64_C(1124073472),	// BRIND
    UINT64_C(268435456),	// BRNEG
    UINT64_C(285212672),	// BRNZ
    UINT64_C(319291392),	// BRNZDEC
    UINT64_C(301989888),	// BRPOS
    UINT64_C(318767104),	// BRZ
    UINT64_C(402653184),	// CALL
    UINT64_C(1107304448),	// CLZ
    UINT64_C(1140850946),	// CMPEQ
    UINT64_C(671088640),	// CMPEQ_SI
    UINT64_C(637534208),	// CMPEQ_ZI
    UINT64_C(1140850947),	// CMPNE
    UINT64_C(1140851200),	// CMPSLT
    UINT64_C(687865856),	// CMPSLT_SI
    UINT64_C(1140851201),	// CMPULT
    UINT64_C(704643072),	// CMPULT_ZI
    UINT64_C(1107300352),	// CMS
    UINT64_C(1124077568),	// EXITNEG
    UINT64_C(1124081664),	// EXITNZ
    UINT64_C(1124085760),	// EXITPOS
    UINT64_C(1124089856),	// EXITZ
    UINT64_C(1375732736),	// F16TOF32
    UINT64_C(1476395789),	// F16V2ABSADD
    UINT64_C(1476395529),	// F16V2ABSMAX
    UINT64_C(1476395009),	// F16V2ADD
    UINT64_C(1476919297),	// F16V2ADD_BL
    UINT64_C(1477181441),	// F16V2ADD_BU
    UINT64_C(1476396045),	// F16V2CLAMP
    UINT64_C(1375742464),	// F16V2CLASS
    UINT64_C(1509950208),	// F16V2CMAC
    UINT64_C(1476395021),	// F16V2CMPEQ
    UINT64_C(1476919309),	// F16V2CMPEQ_BL
    UINT64_C(1477181453),	// F16V2CMPEQ_BU
    UINT64_C(1476395265),	// F16V2CMPGE
    UINT64_C(1476919553),	// F16V2CMPGE_BL
    UINT64_C(1477181697),	// F16V2CMPGE_BU
    UINT64_C(1476395269),	// F16V2CMPGT
    UINT64_C(1476919557),	// F16V2CMPGT_BL
    UINT64_C(1477181701),	// F16V2CMPGT_BU
    UINT64_C(1476395273),	// F16V2CMPLE
    UINT64_C(1476919561),	// F16V2CMPLE_BL
    UINT64_C(1477181705),	// F16V2CMPLE_BU
    UINT64_C(1476395277),	// F16V2CMPLT
    UINT64_C(1476919565),	// F16V2CMPLT_BL
    UINT64_C(1477181709),	// F16V2CMPLT_BU
    UINT64_C(1476395521),	// F16V2CMPNE
    UINT64_C(1476919809),	// F16V2CMPNE_BL
    UINT64_C(1477181953),	// F16V2CMPNE_BU
    UINT64_C(1375744512),	// F16V2EXP
    UINT64_C(1375740416),	// F16V2EXP2
    UINT64_C(1493192704),	// F16V2GINA
    UINT64_C(1342177792),	// F16V2GRAND
    UINT64_C(1375736320),	// F16V2LN
    UINT64_C(1375732224),	// F16V2LOG2
    UINT64_C(1476395525),	// F16V2MAX
    UINT64_C(1375758848),	// F16V2MAXC
    UINT64_C(1476395533),	// F16V2MIN
    UINT64_C(1476395777),	// F16V2MUL
    UINT64_C(1476920065),	// F16V2MUL_BL
    UINT64_C(1477182209),	// F16V2MUL_BU
    UINT64_C(1375754752),	// F16V2SIGMOID
    UINT64_C(1476395781),	// F16V2SUB
    UINT64_C(1476920069),	// F16V2SUB_BL
    UINT64_C(1477182213),	// F16V2SUB_BU
    UINT64_C(1375750656),	// F16V2SUFROMUI
    UINT64_C(1375748608),	// F16V2SUM
    UINT64_C(1375752704),	// F16V2TANH
    UINT64_C(1375736832),	// F16V2TOF32
    UINT64_C(1375759616),	// F16V2TOF8
    UINT64_C(1493206016),	// F16V4ABSACC
    UINT64_C(1476395790),	// F16V4ABSADD
    UINT64_C(1476395530),	// F16V4ABSMAX
    UINT64_C(1493204992),	// F16V4ACC
    UINT64_C(1476395010),	// F16V4ADD
    UINT64_C(1476919298),	// F16V4ADD_BL
    UINT64_C(1477181442),	// F16V4ADD_BU
    UINT64_C(1476396046),	// F16V4CLAMP
    UINT64_C(1375743488),	// F16V4CLASS
    UINT64_C(1509949952),	// F16V4CMAC
    UINT64_C(1476395022),	// F16V4CMPEQ
    UINT64_C(1476919310),	// F16V4CMPEQ_BL
    UINT64_C(1477181454),	// F16V4CMPEQ_BU
    UINT64_C(1476395266),	// F16V4CMPGE
    UINT64_C(1476919554),	// F16V4CMPGE_BL
    UINT64_C(1477181698),	// F16V4CMPGE_BU
    UINT64_C(1476395270),	// F16V4CMPGT
    UINT64_C(1476919558),	// F16V4CMPGT_BL
    UINT64_C(1477181702),	// F16V4CMPGT_BU
    UINT64_C(1476395274),	// F16V4CMPLE
    UINT64_C(1476919562),	// F16V4CMPLE_BL
    UINT64_C(1477181706),	// F16V4CMPLE_BU
    UINT64_C(1476395278),	// F16V4CMPLT
    UINT64_C(1476919566),	// F16V4CMPLT_BL
    UINT64_C(1477181710),	// F16V4CMPLT_BU
    UINT64_C(1476395522),	// F16V4CMPNE
    UINT64_C(1476919810),	// F16V4CMPNE_BL
    UINT64_C(1477181954),	// F16V4CMPNE_BU
    UINT64_C(1342178304),	// F16V4GACC
    UINT64_C(1526726912),	// F16V4HIHOAMP
    UINT64_C(1526726656),	// F16V4HIHOSLIC
    UINT64_C(1526728512),	// F16V4HIHOV4AMP
    UINT64_C(1526728256),	// F16V4HIHOV4SLIC
    UINT64_C(1526728704),	// F16V4ISTACC
    UINT64_C(1476395526),	// F16V4MAX
    UINT64_C(1375759872),	// F16V4MAXC
    UINT64_C(1476395534),	// F16V4MIN
    UINT64_C(1476395018),	// F16V4MIX
    UINT64_C(1476395778),	// F16V4MUL
    UINT64_C(1476920066),	// F16V4MUL_BL
    UINT64_C(1477182210),	// F16V4MUL_BU
    UINT64_C(1476396298),	// F16V4RMASK
    UINT64_C(1526727936),	// F16V4SIHOAMP
    UINT64_C(1526727680),	// F16V4SIHOSLIC
    UINT64_C(1526728448),	// F16V4SISOAMP
    UINT64_C(1526728192),	// F16V4SISOSLIC
    UINT64_C(1358956800),	// F16V4STACC
    UINT64_C(1476395782),	// F16V4SUB
    UINT64_C(1476920070),	// F16V4SUB_BL
    UINT64_C(1477182214),	// F16V4SUB_BU
    UINT64_C(1375751680),	// F16V4SUFROMUI
    UINT64_C(1375749632),	// F16V4SUM
    UINT64_C(1493206272),	// F16V8ABSACC
    UINT64_C(1493205248),	// F16V8ACC
    UINT64_C(1493207296),	// F16V8SQACC
    UINT64_C(1375757824),	// F16V8TOF8
    UINT64_C(1476395016),	// F32ABSADD
    UINT64_C(1476395528),	// F32ABSMAX
    UINT64_C(1476395008),	// F32ADD
    UINT64_C(1476396044),	// F32CLAMP
    UINT64_C(1375742208),	// F32CLASS
    UINT64_C(1476395020),	// F32CMPEQ
    UINT64_C(1476395264),	// F32CMPGE
    UINT64_C(1476395268),	// F32CMPGT
    UINT64_C(1476395272),	// F32CMPLE
    UINT64_C(1476395276),	// F32CMPLT
    UINT64_C(1476395520),	// F32CMPNE
    UINT64_C(1476396288),	// F32DIV
    UINT64_C(1375744256),	// F32EXP
    UINT64_C(1375740160),	// F32EXP2
    UINT64_C(1375760384),	// F32FROMI32
    UINT64_C(1375731712),	// F32FROMUI32
    UINT64_C(1358954496),	// F32INT
    UINT64_C(1375736064),	// F32LN
    UINT64_C(1375731968),	// F32LOG2
    UINT64_C(1509949824),	// F32MAC
    UINT64_C(1476395524),	// F32MAX
    UINT64_C(1476395532),	// F32MIN
    UINT64_C(1476395776),	// F32MUL
    UINT64_C(1375734272),	// F32OORX
    UINT64_C(1375734528),	// F32OOX
    UINT64_C(1375754496),	// F32SIGMOID
    UINT64_C(1526730496),	// F32SISOAMP
    UINT64_C(1526730240),	// F32SISOSLIC
    UINT64_C(1526730560),	// F32SISOV2AMP
    UINT64_C(1375756544),	// F32SQRT
    UINT64_C(1476395780),	// F32SUB
    UINT64_C(1375750400),	// F32SUFROMUI
    UINT64_C(1375752448),	// F32TANH
    UINT64_C(1375745280),	// F32TOF16
    UINT64_C(1375748096),	// F32TOI32
    UINT64_C(1375752192),	// F32TOUI32
    UINT64_C(1476395791),	// F32V2ABSADD
    UINT64_C(1476395531),	// F32V2ABSMAX
    UINT64_C(1476395011),	// F32V2ADD
    UINT64_C(1476919299),	// F32V2ADD_BL
    UINT64_C(1509952512),	// F32V2AOP
    UINT64_C(1476395019),	// F32V2AXPY
    UINT64_C(1476396047),	// F32V2CLAMP
    UINT64_C(1375743744),	// F32V2CLASS
    UINT64_C(1476395023),	// F32V2CMPEQ
    UINT64_C(1476919311),	// F32V2CMPEQ_BL
    UINT64_C(1476395267),	// F32V2CMPGE
    UINT64_C(1476919555),	// F32V2CMPGE_BL
    UINT64_C(1476395271),	// F32V2CMPGT
    UINT64_C(1476919559),	// F32V2CMPGT_BL
    UINT64_C(1476395275),	// F32V2CMPLE
    UINT64_C(1476919563),	// F32V2CMPLE_BL
    UINT64_C(1476395279),	// F32V2CMPLT
    UINT64_C(1476919567),	// F32V2CMPLT_BL
    UINT64_C(1476395523),	// F32V2CMPNE
    UINT64_C(1476919811),	// F32V2CMPNE_BL
    UINT64_C(1493188608),	// F32V2GINA
    UINT64_C(1342178048),	// F32V2GRAND
    UINT64_C(1509949568),	// F32V2MAC
    UINT64_C(1476395527),	// F32V2MAX
    UINT64_C(1476395535),	// F32V2MIN
    UINT64_C(1476395779),	// F32V2MUL
    UINT64_C(1476920067),	// F32V2MUL_BL
    UINT64_C(1476396299),	// F32V2RMASK
    UINT64_C(1476395783),	// F32V2SUB
    UINT64_C(1476920071),	// F32V2SUB_BL
    UINT64_C(1375750912),	// F32V2SUFROMUI
    UINT64_C(1375758080),	// F32V2TOF16
    UINT64_C(1493206528),	// F32V4ABSACC
    UINT64_C(1493205504),	// F32V4ACC
    UINT64_C(1493207552),	// F32V4SQACC
    UINT64_C(1375757568),	// F32V4TOF16
    UINT64_C(1375759360),	// F8V2TOF16
    UINT64_C(1375742720),	// F8V4CLASS
    UINT64_C(1375758336),	// F8V4TOF16
    UINT64_C(1526729024),	// F8V8HIHOV4AMP
    UINT64_C(1526729280),	// F8V8HIHOV4SLIC
    UINT64_C(1090519040),	// GET
    UINT64_C(1291847685),	// LD128
    UINT64_C(1090572288),	// LD128PUTCS
    UINT64_C(1191182851),	// LD128STEP
    UINT64_C(503319040),	// LD128STEP_SI
    UINT64_C(184549376),	// LD128_ZI
    UINT64_C(1174405120),	// LD2X64PACE
    UINT64_C(1442842624),	// LD2XST64PACE
    UINT64_C(1291845632),	// LD32
    UINT64_C(1191182592),	// LD32STEP
    UINT64_C(1191182593),	// LD32STEP_A
    UINT64_C(469762304),	// LD32STEP_SI
    UINT64_C(503316736),	// LD32STEP_SI_A
    UINT64_C(1291847680),	// LD32_A
    UINT64_C(16777216),	// LD32_ZI
    UINT64_C(134217728),	// LD32_ZI_A
    UINT64_C(1191184131),	// LD64A32
    UINT64_C(1174405888),	// LD64A32PACE
    UINT64_C(1174405632),	// LD64B16PACE
    UINT64_C(1090568192),	// LD64PUTCS
    UINT64_C(1191182849),	// LD64STEP_A
    UINT64_C(503316992),	// LD64STEP_SI_A
    UINT64_C(1291847681),	// LD64_A
    UINT64_C(150994944),	// LD64_ZI_A
    UINT64_C(1291847940),	// LDB16
    UINT64_C(1157630208),	// LDB16B16
    UINT64_C(1191183873),	// LDB16STEP
    UINT64_C(503318016),	// LDB16STEP_SI
    UINT64_C(234881024),	// LDB16_ZI
    UINT64_C(1291845644),	// LDB8
    UINT64_C(33554432),	// LDB8_ZI
    UINT64_C(1157630464),	// LDD16A32
    UINT64_C(1157630720),	// LDD16A64
    UINT64_C(1157630976),	// LDD16B16
    UINT64_C(1157629952),	// LDD16V2A32
    UINT64_C(1291845888),	// LDS16
    UINT64_C(1191183360),	// LDS16STEP
    UINT64_C(469763072),	// LDS16STEP_SI
    UINT64_C(67108864),	// LDS16_ZI
    UINT64_C(1291845889),	// LDS8
    UINT64_C(1191183616),	// LDS8STEP
    UINT64_C(469763328),	// LDS8STEP_SI
    UINT64_C(83886080),	// LDS8_ZI
    UINT64_C(1442840832),	// LDST64PACE
    UINT64_C(1291845892),	// LDZ16
    UINT64_C(1191183872),	// LDZ16STEP
    UINT64_C(469763584),	// LDZ16STEP_SI
    UINT64_C(100663296),	// LDZ16_ZI
    UINT64_C(1291845893),	// LDZ8
    UINT64_C(1191184128),	// LDZ8STEP
    UINT64_C(469763840),	// LDZ8STEP_SI
    UINT64_C(117440512),	// LDZ8_ZI
    UINT64_C(1140851202),	// MAX
    UINT64_C(805306368),	// MAX_SI
    UINT64_C(771751936),	// MAX_ZI
    UINT64_C(1140851203),	// MIN
    UINT64_C(855638016),	// MIN_SI
    UINT64_C(822083584),	// MIN_ZI
    UINT64_C(1191184896),	// MOVZ
    UINT64_C(1140851456),	// MUL
    UINT64_C(905969664),	// MUL_SI
    UINT64_C(1375762432),	// NOT
    UINT64_C(1375762688),	// NOT64
    UINT64_C(1140851457),	// OR
    UINT64_C(1476398593),	// OR64
    UINT64_C(1476398592),	// OR_A
    UINT64_C(1107345408),	// OR_IZ
    UINT64_C(1375784960),	// OR_IZ_A
    UINT64_C(1107333120),	// OR_ZI
    UINT64_C(1375768576),	// OR_ZI_A
    UINT64_C(1107308544),	// POPC
    UINT64_C(1124106240),	// PUT
    UINT64_C(1140851458),	// ROLL16
    UINT64_C(1476396548),	// ROLL16_A
    UINT64_C(1476396551),	// ROLL32
    UINT64_C(1140851459),	// ROLL8L
    UINT64_C(1476396549),	// ROLL8L_1
    UINT64_C(1140851712),	// ROLL8R
    UINT64_C(1476396550),	// ROLL8R_1
    UINT64_C(1124114432),	// RPT
    UINT64_C(1073741824),	// RPT_ZI
    UINT64_C(1124073472),	// RTN
    UINT64_C(335544320),	// RUN
    UINT64_C(352321536),	// RUNALL
    UINT64_C(419430400),	// SETZI
    UINT64_C(436207616),	// SETZI_A
    UINT64_C(1140851713),	// SHL
    UINT64_C(1107337216),	// SHL_ZI
    UINT64_C(1140851714),	// SHR
    UINT64_C(1140851715),	// SHRS
    UINT64_C(1107353600),	// SHRS_ZI
    UINT64_C(1107349504),	// SHR_ZI
    UINT64_C(1140851968),	// SHUF8X8HI
    UINT64_C(1476397056),	// SHUF8X8HI_1
    UINT64_C(1140851969),	// SHUF8X8LO
    UINT64_C(1476397057),	// SHUF8X8LO_1
    UINT64_C(1140851970),	// SORT4X16HI
    UINT64_C(1476396552),	// SORT4X16HI_A
    UINT64_C(1140851971),	// SORT4X16LO
    UINT64_C(1476396556),	// SORT4X16LO_A
    UINT64_C(1477182988),	// SORT4X16LO_BU
    UINT64_C(1476396555),	// SORT4X32HI
    UINT64_C(1476396559),	// SORT4X32LO
    UINT64_C(1107312640),	// SORT8
    UINT64_C(1140852224),	// SORT8X8HI
    UINT64_C(1476397058),	// SORT8X8HI_1
    UINT64_C(1140852225),	// SORT8X8LO
    UINT64_C(1476397059),	// SORT8X8LO_1
    UINT64_C(1375763200),	// SORT8_1
    UINT64_C(1426063360),	// ST32STEP_A
    UINT64_C(1308622848),	// ST32STEP_SI
    UINT64_C(1543503872),	// ST32STEP_SI_A
    UINT64_C(1409286144),	// ST32_A
    UINT64_C(1325400064),	// ST32_ZI
    UINT64_C(1577058304),	// ST32_ZI_A
    UINT64_C(1543504384),	// ST64PACE
    UINT64_C(1426063616),	// ST64STEP_A
    UINT64_C(1543504128),	// ST64STEP_SI_A
    UINT64_C(1409286400),	// ST64_A
    UINT64_C(1593835520),	// ST64_ZI_A
    UINT64_C(1275068416),	// STM32
    UINT64_C(1191184640),	// STM32STEP
    UINT64_C(1140852226),	// SUB
    UINT64_C(956301312),	// SUB_SI
    UINT64_C(922746880),	// SUB_ZI
    UINT64_C(1107316736),	// SWAP8
    UINT64_C(1375763456),	// SWAP8_1
    UINT64_C(1291845633),	// TAPACK
    UINT64_C(1098911744),	// TRAP
    UINT64_C(1358956544),	// UGET
    UINT64_C(1358987264),	// UPUT
    UINT64_C(1342177280),	// URAND32
    UINT64_C(1342177536),	// URAND64
    UINT64_C(1140852480),	// XNOR
    UINT64_C(1140852481),	// XOR
    UINT64_C(0)
  };
  const unsigned opcode = MI.getOpcode();
  uint64_t Value = InstBits[opcode];
  uint64_t op = 0;
  (void)op;  // suppress warning
  switch (opcode) {
    case Colossus::F8V8HIHOV4AMP:
    case Colossus::F8V8HIHOV4SLIC:
    case Colossus::F16V4HIHOV4AMP:
    case Colossus::F16V4HIHOV4SLIC:
    case Colossus::F16V4ISTACC:
    case Colossus::F16V4SISOAMP:
    case Colossus::F16V4SISOSLIC: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(63);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F32V2GINA: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(4095);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F32SISOAMP:
    case Colossus::F32SISOSLIC:
    case Colossus::F32SISOV2AMP: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(63);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4STACC: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4ABSACC:
    case Colossus::F16V4ACC: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4CMAC:
    case Colossus::F32V2MAC: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F32V2AOP: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4GACC:
    case Colossus::F32V2GRAND:
    case Colossus::URAND64: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4SUFROMUI:
    case Colossus::F16V4SUM:
    case Colossus::F32V2SUFROMUI:
    case Colossus::NOT64: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::AND64:
    case Colossus::ANDC64:
    case Colossus::F16V4ABSADD:
    case Colossus::F16V4ABSMAX:
    case Colossus::F16V4ADD:
    case Colossus::F16V4CMPEQ:
    case Colossus::F16V4CMPGE:
    case Colossus::F16V4CMPGT:
    case Colossus::F16V4CMPLE:
    case Colossus::F16V4CMPLT:
    case Colossus::F16V4CMPNE:
    case Colossus::F16V4MAX:
    case Colossus::F16V4MIN:
    case Colossus::F16V4MIX:
    case Colossus::F16V4MUL:
    case Colossus::F16V4SUB:
    case Colossus::F32V2ABSADD:
    case Colossus::F32V2ABSMAX:
    case Colossus::F32V2ADD:
    case Colossus::F32V2AXPY:
    case Colossus::F32V2CLAMP:
    case Colossus::F32V2CMPEQ:
    case Colossus::F32V2CMPGE:
    case Colossus::F32V2CMPGT:
    case Colossus::F32V2CMPLE:
    case Colossus::F32V2CMPLT:
    case Colossus::F32V2CMPNE:
    case Colossus::F32V2MAX:
    case Colossus::F32V2MIN:
    case Colossus::F32V2MUL:
    case Colossus::F32V2SUB:
    case Colossus::OR64:
    case Colossus::ROLL32:
    case Colossus::SORT4X32HI:
    case Colossus::SORT4X32LO: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4CLAMP:
    case Colossus::F16V4RMASK:
    case Colossus::F32V2RMASK: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V8TOF8:
    case Colossus::F32V4TOF16: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getARQuadEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F8V4TOF16:
    case Colossus::F16V2TOF32: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4ADD_BL:
    case Colossus::F16V4ADD_BU:
    case Colossus::F16V4CMPEQ_BL:
    case Colossus::F16V4CMPEQ_BU:
    case Colossus::F16V4CMPGE_BL:
    case Colossus::F16V4CMPGE_BU:
    case Colossus::F16V4CMPGT_BL:
    case Colossus::F16V4CMPGT_BU:
    case Colossus::F16V4CMPLE_BL:
    case Colossus::F16V4CMPLE_BU:
    case Colossus::F16V4CMPLT_BL:
    case Colossus::F16V4CMPLT_BU:
    case Colossus::F16V4CMPNE_BL:
    case Colossus::F16V4CMPNE_BU:
    case Colossus::F16V4MUL_BL:
    case Colossus::F16V4MUL_BU:
    case Colossus::F16V4SUB_BL:
    case Colossus::F16V4SUB_BU:
    case Colossus::F32V2ADD_BL:
    case Colossus::F32V2CMPEQ_BL:
    case Colossus::F32V2CMPGE_BL:
    case Colossus::F32V2CMPGT_BL:
    case Colossus::F32V2CMPLE_BL:
    case Colossus::F32V2CMPLT_BL:
    case Colossus::F32V2CMPNE_BL:
    case Colossus::F32V2MUL_BL:
    case Colossus::F32V2SUB_BL: {
      // op: op0
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V8ABSACC:
    case Colossus::F16V8ACC:
    case Colossus::F16V8SQACC:
    case Colossus::F32V4ABSACC:
    case Colossus::F32V4ACC:
    case Colossus::F32V4SQACC: {
      // op: op0
      op = getARQuadEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::TRAP: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4SIHOAMP:
    case Colossus::F16V4SIHOSLIC: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(63);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4HIHOAMP:
    case Colossus::F16V4HIHOSLIC: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(63);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ANDC_IZ_A:
    case Colossus::AND_IZ_A:
    case Colossus::OR_IZ:
    case Colossus::OR_IZ_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getImm12IZValue(MI, 2, Fixups, STI);
      op &= UINT64_C(4095);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F32INT: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ANDC_ZI:
    case Colossus::ANDC_ZI_A:
    case Colossus::AND_ZI:
    case Colossus::AND_ZI_A:
    case Colossus::F16V2GINA:
    case Colossus::OR_ZI:
    case Colossus::OR_ZI_A:
    case Colossus::SHL_ZI:
    case Colossus::SHRS_ZI:
    case Colossus::SHR_ZI: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(4095);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ADD_SI:
    case Colossus::ADD_ZI:
    case Colossus::CMPEQ_SI:
    case Colossus::CMPEQ_ZI:
    case Colossus::CMPSLT_SI:
    case Colossus::MAX_SI:
    case Colossus::MAX_ZI:
    case Colossus::MIN_SI:
    case Colossus::MIN_ZI:
    case Colossus::MUL_SI:
    case Colossus::SUB_SI:
    case Colossus::SUB_ZI: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(65535);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::CMPULT_ZI: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getRel16OpValue(MI, 2, Fixups, STI);
      op &= UINT64_C(65535);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ATOM: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::GET:
    case Colossus::UGET: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::EXITNEG:
    case Colossus::EXITNZ:
    case Colossus::EXITPOS:
    case Colossus::EXITZ: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      break;
    }
    case Colossus::BRIND:
    case Colossus::RTN: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V2CMAC:
    case Colossus::F32MAC: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::RUNALL: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= (op & UINT64_C(4095));
      break;
    }
    case Colossus::RUN: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getRunOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= (op & UINT64_C(4095));
      break;
    }
    case Colossus::PUT:
    case Colossus::UPUT: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::CALL: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getRel19S2OpValue(MI, 1, Fixups, STI);
      op &= UINT64_C(1048575);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::BRNEG:
    case Colossus::BRNZ:
    case Colossus::BRPOS:
    case Colossus::BRZ: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getRel19S2OpValue(MI, 1, Fixups, STI);
      op &= UINT64_C(524287);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::BRNZDEC: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getRel19S2OpValue(MI, 2, Fixups, STI);
      op &= UINT64_C(524287);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::SETZI:
    case Colossus::SETZI_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getRel20OpValue(MI, 1, Fixups, STI);
      op &= UINT64_C(1048575);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::RPT: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getRel8OpValue(MI, 1, Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V2GRAND:
    case Colossus::URAND32: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F16V4CLASS:
    case Colossus::F16V4MAXC:
    case Colossus::F32V2CLASS:
    case Colossus::F32V2TOF16: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ABS:
    case Colossus::BITREV8:
    case Colossus::CLZ:
    case Colossus::CMS:
    case Colossus::F8V2TOF16:
    case Colossus::F8V4CLASS:
    case Colossus::F16TOF32:
    case Colossus::F16V2CLASS:
    case Colossus::F16V2EXP:
    case Colossus::F16V2EXP2:
    case Colossus::F16V2LN:
    case Colossus::F16V2LOG2:
    case Colossus::F16V2MAXC:
    case Colossus::F16V2SIGMOID:
    case Colossus::F16V2SUFROMUI:
    case Colossus::F16V2SUM:
    case Colossus::F16V2TANH:
    case Colossus::F16V2TOF8:
    case Colossus::F32CLASS:
    case Colossus::F32EXP:
    case Colossus::F32EXP2:
    case Colossus::F32FROMI32:
    case Colossus::F32FROMUI32:
    case Colossus::F32LN:
    case Colossus::F32LOG2:
    case Colossus::F32OORX:
    case Colossus::F32OOX:
    case Colossus::F32SIGMOID:
    case Colossus::F32SQRT:
    case Colossus::F32SUFROMUI:
    case Colossus::F32TANH:
    case Colossus::F32TOF16:
    case Colossus::F32TOI32:
    case Colossus::F32TOUI32:
    case Colossus::NOT:
    case Colossus::POPC:
    case Colossus::SORT8:
    case Colossus::SORT8_1:
    case Colossus::SWAP8:
    case Colossus::SWAP8_1: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::F32CLAMP: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ADD:
    case Colossus::AND:
    case Colossus::ANDC:
    case Colossus::ANDC_A:
    case Colossus::AND_A:
    case Colossus::CMPEQ:
    case Colossus::CMPNE:
    case Colossus::CMPSLT:
    case Colossus::CMPULT:
    case Colossus::F16V2ABSADD:
    case Colossus::F16V2ABSMAX:
    case Colossus::F16V2ADD:
    case Colossus::F16V2ADD_BL:
    case Colossus::F16V2ADD_BU:
    case Colossus::F16V2CLAMP:
    case Colossus::F16V2CMPEQ:
    case Colossus::F16V2CMPEQ_BL:
    case Colossus::F16V2CMPEQ_BU:
    case Colossus::F16V2CMPGE:
    case Colossus::F16V2CMPGE_BL:
    case Colossus::F16V2CMPGE_BU:
    case Colossus::F16V2CMPGT:
    case Colossus::F16V2CMPGT_BL:
    case Colossus::F16V2CMPGT_BU:
    case Colossus::F16V2CMPLE:
    case Colossus::F16V2CMPLE_BL:
    case Colossus::F16V2CMPLE_BU:
    case Colossus::F16V2CMPLT:
    case Colossus::F16V2CMPLT_BL:
    case Colossus::F16V2CMPLT_BU:
    case Colossus::F16V2CMPNE:
    case Colossus::F16V2CMPNE_BL:
    case Colossus::F16V2CMPNE_BU:
    case Colossus::F16V2MAX:
    case Colossus::F16V2MIN:
    case Colossus::F16V2MUL:
    case Colossus::F16V2MUL_BL:
    case Colossus::F16V2MUL_BU:
    case Colossus::F16V2SUB:
    case Colossus::F16V2SUB_BL:
    case Colossus::F16V2SUB_BU:
    case Colossus::F32ABSADD:
    case Colossus::F32ABSMAX:
    case Colossus::F32ADD:
    case Colossus::F32CMPEQ:
    case Colossus::F32CMPGE:
    case Colossus::F32CMPGT:
    case Colossus::F32CMPLE:
    case Colossus::F32CMPLT:
    case Colossus::F32CMPNE:
    case Colossus::F32DIV:
    case Colossus::F32MAX:
    case Colossus::F32MIN:
    case Colossus::F32MUL:
    case Colossus::F32SUB:
    case Colossus::MAX:
    case Colossus::MIN:
    case Colossus::MUL:
    case Colossus::OR:
    case Colossus::OR_A:
    case Colossus::ROLL8L:
    case Colossus::ROLL8L_1:
    case Colossus::ROLL8R:
    case Colossus::ROLL8R_1:
    case Colossus::ROLL16:
    case Colossus::ROLL16_A:
    case Colossus::SHL:
    case Colossus::SHR:
    case Colossus::SHRS:
    case Colossus::SHUF8X8HI:
    case Colossus::SHUF8X8HI_1:
    case Colossus::SHUF8X8LO:
    case Colossus::SHUF8X8LO_1:
    case Colossus::SORT4X16HI:
    case Colossus::SORT4X16HI_A:
    case Colossus::SORT4X16LO:
    case Colossus::SORT4X16LO_A:
    case Colossus::SORT4X16LO_BU:
    case Colossus::SORT8X8HI:
    case Colossus::SORT8X8HI_1:
    case Colossus::SORT8X8LO:
    case Colossus::SORT8X8LO_1:
    case Colossus::SUB:
    case Colossus::XNOR:
    case Colossus::XOR: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD64PUTCS:
    case Colossus::LD128PUTCS: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::RPT_ZI: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(4095);
      op <<= 8;
      Value |= op;
      // op: op1
      op = getRel8OpValue(MI, 1, Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ST64PACE:
    case Colossus::ST64STEP_SI_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(240)) >> 4;
      // op: op3
      op = getARPairEncoding(MI, 4, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ST32STEP_SI_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(240)) >> 4;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ST64STEP_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getARPairEncoding(MI, 4, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ST32STEP_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::ST32STEP_SI: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::TAPACK: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LDST64PACE: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getARPairEncoding(MI, 4, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op4
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(15);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD2XST64PACE: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getARQuadEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(14);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getARPairEncoding(MI, 4, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op4
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(48)) << 4;
      Value |= (op & UINT64_C(15));
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD64STEP_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD64A32:
    case Colossus::LD128STEP: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getARQuadEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD32STEP:
    case Colossus::LD32STEP_A:
    case Colossus::LDB16STEP:
    case Colossus::LDS8STEP:
    case Colossus::LDS16STEP:
    case Colossus::LDZ8STEP:
    case Colossus::LDZ16STEP: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD64STEP_SI_A: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: op3
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD128STEP_SI: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: op3
      op = getARQuadEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD32STEP_SI:
    case Colossus::LD32STEP_SI_A:
    case Colossus::LDB16STEP_SI:
    case Colossus::LDS8STEP_SI:
    case Colossus::LDS16STEP_SI:
    case Colossus::LDZ8STEP_SI:
    case Colossus::LDZ16STEP_SI: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(255);
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD2X64PACE: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op4
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(15);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD64A32PACE:
    case Colossus::LD64B16PACE: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getARPairEncoding(MI, 1, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: op4
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      op &= UINT64_C(15);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LDB16B16:
    case Colossus::LDD16A64: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getARPairEncoding(MI, 2, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LDD16A32:
    case Colossus::LDD16B16:
    case Colossus::LDD16V2A32: {
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::BR: {
      // op: op0
      op = getRel19S2OpValue(MI, 0, Fixups, STI);
      op &= UINT64_C(524287);
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::STM32: {
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrrEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(240)) << 8;
      break;
    }
    case Colossus::MOVZ:
    case Colossus::STM32STEP: {
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 12;
      Value |= op;
      // op: op0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 20;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      break;
    }
    case Colossus::LD64_ZI_A: {
      // op: op3
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrriEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(240)) << 8;
      Value |= (op & UINT64_C(1048320)) >> 8;
      break;
    }
    case Colossus::ST64_ZI_A: {
      // op: op3
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrriEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= (op & UINT64_C(240)) << 8;
      Value |= (op & UINT64_C(983040)) >> 8;
      Value |= (op & UINT64_C(3840)) >> 8;
      break;
    }
    case Colossus::LD64_A:
    case Colossus::ST64_A: {
      // op: op3
      op = getARPairEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrrrEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(4080)) << 8;
      break;
    }
    case Colossus::LD128_ZI: {
      // op: op3
      op = getARQuadEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrriEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(240)) << 8;
      Value |= (op & UINT64_C(1048320)) >> 8;
      break;
    }
    case Colossus::LD128: {
      // op: op3
      op = getARQuadEncoding(MI, 0, Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrrrEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(4080)) << 8;
      break;
    }
    case Colossus::LD32_ZI:
    case Colossus::LD32_ZI_A:
    case Colossus::LDB8_ZI:
    case Colossus::LDB16_ZI:
    case Colossus::LDS8_ZI:
    case Colossus::LDS16_ZI:
    case Colossus::LDZ8_ZI:
    case Colossus::LDZ16_ZI:
    case Colossus::ST32_ZI: {
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 16;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrriEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(240)) << 8;
      Value |= (op & UINT64_C(1048320)) >> 8;
      break;
    }
    case Colossus::ST32_ZI_A: {
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrriEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= (op & UINT64_C(240)) << 8;
      Value |= (op & UINT64_C(983040)) >> 8;
      Value |= (op & UINT64_C(3840)) >> 8;
      break;
    }
    case Colossus::LD32:
    case Colossus::LD32_A:
    case Colossus::LDB8:
    case Colossus::LDB16:
    case Colossus::LDS8:
    case Colossus::LDS16:
    case Colossus::LDZ8:
    case Colossus::LDZ16:
    case Colossus::ST32_A: {
      // op: op3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      op &= UINT64_C(15);
      op <<= 4;
      Value |= op;
      // op: coissue
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      op &= UINT64_C(1);
      op <<= 31;
      Value |= op;
      // op: addr
      op = getMEMrrrEncoding(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      Value |= (op & UINT64_C(4080)) << 8;
      break;
    }
  default:
    std::string msg;
    raw_string_ostream Msg(msg);
    Msg << "Not supported instr: " << MI;
    report_fatal_error(Msg.str().c_str());
  }
  return Value;
}

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t ColossusMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case Colossus::BR:
    case Colossus::LD64PUTCS:
    case Colossus::LD128PUTCS:
    case Colossus::TRAP: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 0;
      case 1:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::F16V4STACC:
    case Colossus::GET:
    case Colossus::UGET: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 16;
      case 1:
        // op: op1
        return 0;
      case 2:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::F8V8HIHOV4AMP:
    case Colossus::F8V8HIHOV4SLIC:
    case Colossus::F16V4HIHOAMP:
    case Colossus::F16V4HIHOSLIC:
    case Colossus::F16V4HIHOV4AMP:
    case Colossus::F16V4HIHOV4SLIC:
    case Colossus::F16V4ISTACC:
    case Colossus::F16V4SIHOAMP:
    case Colossus::F16V4SIHOSLIC:
    case Colossus::F16V4SISOAMP:
    case Colossus::F16V4SISOSLIC:
    case Colossus::F32SISOAMP:
    case Colossus::F32SISOSLIC:
    case Colossus::F32SISOV2AMP: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 16;
      case 1:
        // op: op1
        return 12;
      case 2:
        // op: op2
        return 20;
      case 3:
        // op: op3
        return 0;
      case 4:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::ADD_SI:
    case Colossus::ADD_ZI:
    case Colossus::ANDC_IZ_A:
    case Colossus::ANDC_ZI:
    case Colossus::ANDC_ZI_A:
    case Colossus::AND_IZ_A:
    case Colossus::AND_ZI:
    case Colossus::AND_ZI_A:
    case Colossus::CMPEQ_SI:
    case Colossus::CMPEQ_ZI:
    case Colossus::CMPSLT_SI:
    case Colossus::CMPULT_ZI:
    case Colossus::F16V2GINA:
    case Colossus::F32INT:
    case Colossus::F32V2GINA:
    case Colossus::MAX_SI:
    case Colossus::MAX_ZI:
    case Colossus::MIN_SI:
    case Colossus::MIN_ZI:
    case Colossus::MUL_SI:
    case Colossus::OR_IZ:
    case Colossus::OR_IZ_A:
    case Colossus::OR_ZI:
    case Colossus::OR_ZI_A:
    case Colossus::SHL_ZI:
    case Colossus::SHRS_ZI:
    case Colossus::SHR_ZI:
    case Colossus::SUB_SI:
    case Colossus::SUB_ZI: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 16;
      case 1:
        // op: op1
        return 20;
      case 2:
        // op: op2
        return 0;
      case 3:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::ATOM: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 16;
      case 1:
        // op: op1
        return 4;
      case 2:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::BRIND:
    case Colossus::F16V4ABSACC:
    case Colossus::F16V4ACC:
    case Colossus::F16V8ABSACC:
    case Colossus::F16V8ACC:
    case Colossus::F16V8SQACC:
    case Colossus::F32V4ABSACC:
    case Colossus::F32V4ACC:
    case Colossus::F32V4SQACC:
    case Colossus::RTN: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 20;
      case 1:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::BRNEG:
    case Colossus::BRNZ:
    case Colossus::BRPOS:
    case Colossus::BRZ:
    case Colossus::CALL:
    case Colossus::PUT:
    case Colossus::RPT:
    case Colossus::SETZI:
    case Colossus::SETZI_A:
    case Colossus::UPUT: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 20;
      case 1:
        // op: op1
        return 0;
      case 2:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::F16V2CMAC:
    case Colossus::F16V4CMAC:
    case Colossus::F32MAC:
    case Colossus::F32V2MAC: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 20;
      case 1:
        // op: op1
        return 12;
      case 2:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::F32V2AOP: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 20;
      case 1:
        // op: op1
        return 12;
      case 2:
        // op: op2
        return 0;
      case 3:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::RUN:
    case Colossus::RUNALL: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 20;
      case 1:
        // op: op1
        return 12;
      case 2:
        // op: op2
        return 0;
      }
      break;
    }
    case Colossus::BRNZDEC: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 20;
      case 2:
        // op: op1
        return 0;
      case 3:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::EXITNEG:
    case Colossus::EXITNZ:
    case Colossus::EXITPOS:
    case Colossus::EXITZ: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 20;
      }
      break;
    }
    case Colossus::F16V2GRAND:
    case Colossus::F16V4GACC:
    case Colossus::F32V2GRAND:
    case Colossus::URAND32:
    case Colossus::URAND64: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 4;
      case 1:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::ABS:
    case Colossus::BITREV8:
    case Colossus::CLZ:
    case Colossus::CMS:
    case Colossus::F8V2TOF16:
    case Colossus::F8V4CLASS:
    case Colossus::F8V4TOF16:
    case Colossus::F16TOF32:
    case Colossus::F16V2CLASS:
    case Colossus::F16V2EXP:
    case Colossus::F16V2EXP2:
    case Colossus::F16V2LN:
    case Colossus::F16V2LOG2:
    case Colossus::F16V2MAXC:
    case Colossus::F16V2SIGMOID:
    case Colossus::F16V2SUFROMUI:
    case Colossus::F16V2SUM:
    case Colossus::F16V2TANH:
    case Colossus::F16V2TOF8:
    case Colossus::F16V2TOF32:
    case Colossus::F16V4CLASS:
    case Colossus::F16V4MAXC:
    case Colossus::F16V4SUFROMUI:
    case Colossus::F16V4SUM:
    case Colossus::F16V8TOF8:
    case Colossus::F32CLASS:
    case Colossus::F32EXP:
    case Colossus::F32EXP2:
    case Colossus::F32FROMI32:
    case Colossus::F32FROMUI32:
    case Colossus::F32LN:
    case Colossus::F32LOG2:
    case Colossus::F32OORX:
    case Colossus::F32OOX:
    case Colossus::F32SIGMOID:
    case Colossus::F32SQRT:
    case Colossus::F32SUFROMUI:
    case Colossus::F32TANH:
    case Colossus::F32TOF16:
    case Colossus::F32TOI32:
    case Colossus::F32TOUI32:
    case Colossus::F32V2CLASS:
    case Colossus::F32V2SUFROMUI:
    case Colossus::F32V2TOF16:
    case Colossus::F32V4TOF16:
    case Colossus::NOT:
    case Colossus::NOT64:
    case Colossus::POPC:
    case Colossus::SORT8:
    case Colossus::SORT8_1:
    case Colossus::SWAP8:
    case Colossus::SWAP8_1: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 4;
      case 1:
        // op: op1
        return 20;
      case 2:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::ADD:
    case Colossus::AND:
    case Colossus::AND64:
    case Colossus::ANDC:
    case Colossus::ANDC64:
    case Colossus::ANDC_A:
    case Colossus::AND_A:
    case Colossus::CMPEQ:
    case Colossus::CMPNE:
    case Colossus::CMPSLT:
    case Colossus::CMPULT:
    case Colossus::F16V2ABSADD:
    case Colossus::F16V2ABSMAX:
    case Colossus::F16V2ADD:
    case Colossus::F16V2ADD_BL:
    case Colossus::F16V2ADD_BU:
    case Colossus::F16V2CLAMP:
    case Colossus::F16V2CMPEQ:
    case Colossus::F16V2CMPEQ_BL:
    case Colossus::F16V2CMPEQ_BU:
    case Colossus::F16V2CMPGE:
    case Colossus::F16V2CMPGE_BL:
    case Colossus::F16V2CMPGE_BU:
    case Colossus::F16V2CMPGT:
    case Colossus::F16V2CMPGT_BL:
    case Colossus::F16V2CMPGT_BU:
    case Colossus::F16V2CMPLE:
    case Colossus::F16V2CMPLE_BL:
    case Colossus::F16V2CMPLE_BU:
    case Colossus::F16V2CMPLT:
    case Colossus::F16V2CMPLT_BL:
    case Colossus::F16V2CMPLT_BU:
    case Colossus::F16V2CMPNE:
    case Colossus::F16V2CMPNE_BL:
    case Colossus::F16V2CMPNE_BU:
    case Colossus::F16V2MAX:
    case Colossus::F16V2MIN:
    case Colossus::F16V2MUL:
    case Colossus::F16V2MUL_BL:
    case Colossus::F16V2MUL_BU:
    case Colossus::F16V2SUB:
    case Colossus::F16V2SUB_BL:
    case Colossus::F16V2SUB_BU:
    case Colossus::F16V4ABSADD:
    case Colossus::F16V4ABSMAX:
    case Colossus::F16V4ADD:
    case Colossus::F16V4ADD_BL:
    case Colossus::F16V4ADD_BU:
    case Colossus::F16V4CLAMP:
    case Colossus::F16V4CMPEQ:
    case Colossus::F16V4CMPEQ_BL:
    case Colossus::F16V4CMPEQ_BU:
    case Colossus::F16V4CMPGE:
    case Colossus::F16V4CMPGE_BL:
    case Colossus::F16V4CMPGE_BU:
    case Colossus::F16V4CMPGT:
    case Colossus::F16V4CMPGT_BL:
    case Colossus::F16V4CMPGT_BU:
    case Colossus::F16V4CMPLE:
    case Colossus::F16V4CMPLE_BL:
    case Colossus::F16V4CMPLE_BU:
    case Colossus::F16V4CMPLT:
    case Colossus::F16V4CMPLT_BL:
    case Colossus::F16V4CMPLT_BU:
    case Colossus::F16V4CMPNE:
    case Colossus::F16V4CMPNE_BL:
    case Colossus::F16V4CMPNE_BU:
    case Colossus::F16V4MAX:
    case Colossus::F16V4MIN:
    case Colossus::F16V4MIX:
    case Colossus::F16V4MUL:
    case Colossus::F16V4MUL_BL:
    case Colossus::F16V4MUL_BU:
    case Colossus::F16V4RMASK:
    case Colossus::F16V4SUB:
    case Colossus::F16V4SUB_BL:
    case Colossus::F16V4SUB_BU:
    case Colossus::F32ABSADD:
    case Colossus::F32ABSMAX:
    case Colossus::F32ADD:
    case Colossus::F32CLAMP:
    case Colossus::F32CMPEQ:
    case Colossus::F32CMPGE:
    case Colossus::F32CMPGT:
    case Colossus::F32CMPLE:
    case Colossus::F32CMPLT:
    case Colossus::F32CMPNE:
    case Colossus::F32DIV:
    case Colossus::F32MAX:
    case Colossus::F32MIN:
    case Colossus::F32MUL:
    case Colossus::F32SUB:
    case Colossus::F32V2ABSADD:
    case Colossus::F32V2ABSMAX:
    case Colossus::F32V2ADD:
    case Colossus::F32V2ADD_BL:
    case Colossus::F32V2AXPY:
    case Colossus::F32V2CLAMP:
    case Colossus::F32V2CMPEQ:
    case Colossus::F32V2CMPEQ_BL:
    case Colossus::F32V2CMPGE:
    case Colossus::F32V2CMPGE_BL:
    case Colossus::F32V2CMPGT:
    case Colossus::F32V2CMPGT_BL:
    case Colossus::F32V2CMPLE:
    case Colossus::F32V2CMPLE_BL:
    case Colossus::F32V2CMPLT:
    case Colossus::F32V2CMPLT_BL:
    case Colossus::F32V2CMPNE:
    case Colossus::F32V2CMPNE_BL:
    case Colossus::F32V2MAX:
    case Colossus::F32V2MIN:
    case Colossus::F32V2MUL:
    case Colossus::F32V2MUL_BL:
    case Colossus::F32V2RMASK:
    case Colossus::F32V2SUB:
    case Colossus::F32V2SUB_BL:
    case Colossus::MAX:
    case Colossus::MIN:
    case Colossus::MUL:
    case Colossus::OR:
    case Colossus::OR64:
    case Colossus::OR_A:
    case Colossus::ROLL8L:
    case Colossus::ROLL8L_1:
    case Colossus::ROLL8R:
    case Colossus::ROLL8R_1:
    case Colossus::ROLL16:
    case Colossus::ROLL16_A:
    case Colossus::ROLL32:
    case Colossus::SHL:
    case Colossus::SHR:
    case Colossus::SHRS:
    case Colossus::SHUF8X8HI:
    case Colossus::SHUF8X8HI_1:
    case Colossus::SHUF8X8LO:
    case Colossus::SHUF8X8LO_1:
    case Colossus::SORT4X16HI:
    case Colossus::SORT4X16HI_A:
    case Colossus::SORT4X16LO:
    case Colossus::SORT4X16LO_A:
    case Colossus::SORT4X16LO_BU:
    case Colossus::SORT4X32HI:
    case Colossus::SORT4X32LO:
    case Colossus::SORT8X8HI:
    case Colossus::SORT8X8HI_1:
    case Colossus::SORT8X8LO:
    case Colossus::SORT8X8LO_1:
    case Colossus::SUB:
    case Colossus::XNOR:
    case Colossus::XOR: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 4;
      case 1:
        // op: op1
        return 20;
      case 2:
        // op: op2
        return 12;
      case 3:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::RPT_ZI: {
      switch (OpNum) {
      case 0:
        // op: op0
        return 8;
      case 1:
        // op: op1
        return 0;
      case 2:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::STM32: {
      switch (OpNum) {
      case 0:
        // op: op2
        return 16;
      case 3:
        // op: coissue
        return 31;
      case 1:
        // op: addr
        return 12;
      }
      break;
    }
    case Colossus::LD32_ZI:
    case Colossus::LD32_ZI_A:
    case Colossus::LD64_ZI_A:
    case Colossus::LD128_ZI:
    case Colossus::LDB8_ZI:
    case Colossus::LDB16_ZI:
    case Colossus::LDS8_ZI:
    case Colossus::LDS16_ZI:
    case Colossus::LDZ8_ZI:
    case Colossus::LDZ16_ZI:
    case Colossus::ST32_ZI: {
      switch (OpNum) {
      case 0:
        // op: op3
        return 16;
      case 4:
        // op: coissue
        return 31;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Colossus::ST32_ZI_A:
    case Colossus::ST64_ZI_A: {
      switch (OpNum) {
      case 0:
        // op: op3
        return 4;
      case 4:
        // op: coissue
        return 31;
      case 1:
        // op: addr
        return 0;
      }
      break;
    }
    case Colossus::LD32:
    case Colossus::LD32_A:
    case Colossus::LD64_A:
    case Colossus::LD128:
    case Colossus::LDB8:
    case Colossus::LDB16:
    case Colossus::LDS8:
    case Colossus::LDS16:
    case Colossus::LDZ8:
    case Colossus::LDZ16:
    case Colossus::ST32_A:
    case Colossus::ST64_A: {
      switch (OpNum) {
      case 0:
        // op: op3
        return 4;
      case 4:
        // op: coissue
        return 31;
      case 1:
        // op: addr
        return 12;
      }
      break;
    }
    case Colossus::ST32STEP_SI: {
      switch (OpNum) {
      case 1:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 3:
        // op: op2
        return 0;
      case 4:
        // op: op3
        return 16;
      case 5:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::ST32STEP_SI_A:
    case Colossus::ST64PACE:
    case Colossus::ST64STEP_SI_A: {
      switch (OpNum) {
      case 1:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 3:
        // op: op2
        return 0;
      case 4:
        // op: op3
        return 4;
      case 5:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::ST32STEP_A:
    case Colossus::ST64STEP_A: {
      switch (OpNum) {
      case 1:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 3:
        // op: op2
        return 16;
      case 4:
        // op: op3
        return 4;
      case 5:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::TAPACK: {
      switch (OpNum) {
      case 1:
        // op: op0
        return 20;
      case 2:
        // op: op1
        return 12;
      case 3:
        // op: op2
        return 16;
      case 0:
        // op: op3
        return 4;
      case 4:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::MOVZ:
    case Colossus::STM32STEP: {
      switch (OpNum) {
      case 1:
        // op: op2
        return 16;
      case 0:
        // op: op1
        return 12;
      case 3:
        // op: op0
        return 20;
      case 4:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::LDST64PACE: {
      switch (OpNum) {
      case 2:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 1:
        // op: op2
        return 16;
      case 4:
        // op: op3
        return 4;
      case 5:
        // op: op4
        return 0;
      case 6:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::LD2XST64PACE: {
      switch (OpNum) {
      case 2:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 1:
        // op: op2
        return 17;
      case 4:
        // op: op3
        return 4;
      case 5:
        // op: op4
        return 0;
      case 6:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::LD32STEP_SI:
    case Colossus::LD32STEP_SI_A:
    case Colossus::LD64STEP_SI_A:
    case Colossus::LD128STEP_SI:
    case Colossus::LDB16STEP_SI:
    case Colossus::LDS8STEP_SI:
    case Colossus::LDS16STEP_SI:
    case Colossus::LDZ8STEP_SI:
    case Colossus::LDZ16STEP_SI: {
      switch (OpNum) {
      case 2:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 4:
        // op: op2
        return 0;
      case 1:
        // op: op3
        return 16;
      case 5:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::LD32STEP:
    case Colossus::LD32STEP_A:
    case Colossus::LD64A32:
    case Colossus::LD64STEP_A:
    case Colossus::LD128STEP:
    case Colossus::LDB16STEP:
    case Colossus::LDS8STEP:
    case Colossus::LDS16STEP:
    case Colossus::LDZ8STEP:
    case Colossus::LDZ16STEP: {
      switch (OpNum) {
      case 2:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 4:
        // op: op2
        return 16;
      case 1:
        // op: op3
        return 4;
      case 5:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::LD2X64PACE:
    case Colossus::LD64A32PACE:
    case Colossus::LD64B16PACE: {
      switch (OpNum) {
      case 3:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 1:
        // op: op2
        return 16;
      case 2:
        // op: op3
        return 4;
      case 5:
        // op: op4
        return 0;
      case 6:
        // op: coissue
        return 31;
      }
      break;
    }
    case Colossus::LDB16B16:
    case Colossus::LDD16A32:
    case Colossus::LDD16A64:
    case Colossus::LDD16B16:
    case Colossus::LDD16V2A32: {
      switch (OpNum) {
      case 3:
        // op: op0
        return 20;
      case 0:
        // op: op1
        return 12;
      case 1:
        // op: op2
        return 16;
      case 2:
        // op: op3
        return 4;
      case 6:
        // op: coissue
        return 31;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET