/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #include #undef GET_REGINFO_ENUM namespace llvm { class MCRegisterClass; extern const MCRegisterClass ColossusMCRegisterClasses[]; namespace Colossus { enum ColossusRegs : unsigned { NoRegister, AOZERO = 1, AQZERO = 2, AZERO = 3, AZEROS = 4, BP = 5, FP = 6, LR = 7, MVERTEX_BASE = 8, MWORKER_BASE = 9, MZERO = 10, SP = 11, A0 = 12, A1 = 13, A2 = 14, A3 = 15, A4 = 16, A5 = 17, A6 = 18, A7 = 19, A8 = 20, A9 = 21, A10 = 22, A11 = 23, A12 = 24, A13 = 25, A14 = 26, ACC0 = 27, ACC1 = 28, ACC2 = 29, ACC3 = 30, ACC4 = 31, ACC5 = 32, ACC6 = 33, ACC7 = 34, ACCD0 = 35, ACCD1 = 36, ACCD2 = 37, ACCD3 = 38, ACCQ0 = 39, ACCQ1 = 40, AD0 = 41, AD1 = 42, AD2 = 43, AD3 = 44, AD4 = 45, AD5 = 46, AD6 = 47, AD7 = 48, AD8 = 49, AD9 = 50, AD10 = 51, AD11 = 52, AD12 = 53, AD13 = 54, AD14 = 55, AO0 = 56, AO1 = 57, AO2 = 58, AO3 = 59, AO4 = 60, AO5 = 61, AO6 = 62, AO7 = 63, AO8 = 64, AO9 = 65, AO10 = 66, AO11 = 67, AO12 = 68, AO13 = 69, AO14 = 70, AQ0 = 71, AQ1 = 72, AQ2 = 73, AQ3 = 74, AQ4 = 75, AQ5 = 76, AQ6 = 77, AQ7 = 78, AQ8 = 79, AQ9 = 80, AQ10 = 81, AQ11 = 82, AQ12 = 83, AQ13 = 84, AQ14 = 85, M0 = 86, M1 = 87, M2 = 88, M3 = 89, M4 = 90, M5 = 91, M6 = 92, M7 = 93, M14 = 94, MD0 = 95, MD1 = 96, MD2 = 97, MD3 = 98, MD4 = 99, MD5 = 100, MD6 = 101, MD7 = 102, NUM_TARGET_REGS // 103 }; } // end namespace Colossus // Register classes namespace Colossus { enum { ARRegClassID = 0, MRRegClassID = 1, ACCRegClassID = 2, ARPairRegClassID = 3, ARPair_with_SubRegHiRegClassID = 4, MRPairRegClassID = 5, ACCPairRegClassID = 6, ARQuadRegClassID = 7, ARQuad_with_QuadHiRegClassID = 8, ACCQuadRegClassID = 9, AROctadRegClassID = 10, AROctad_with_OctadHiRegClassID = 11, AROctad_with_OctadHi_then_QuadHiRegClassID = 12, }; } // end namespace Colossus // Subregister indices namespace Colossus { enum SubRegIndices : uint16_t { NoSubRegister, OctadHi, // 1 OctadLo, // 2 QuadAR0, // 3 QuadAR1, // 4 QuadAR2, // 5 QuadAR3, // 6 QuadHi, // 7 QuadLo, // 8 SubRegHi, // 9 SubRegLo, // 10 QuadHi_then_SubRegHi, // 11 QuadHi_then_SubRegLo, // 12 OctadHi_then_QuadHi, // 13 OctadHi_then_QuadLo, // 14 OctadHi_then_SubRegHi, // 15 OctadHi_then_SubRegLo, // 16 OctadHi_then_QuadHi_then_SubRegHi, // 17 OctadHi_then_QuadHi_then_SubRegLo, // 18 NUM_TARGET_SUBREGS }; } // end namespace Colossus // Register pressure sets enum. namespace Colossus { enum RegisterPressureSets { ACC = 0, AROctad_with_OctadHi_then_QuadHi = 1, AROctad_with_OctadHi = 2, MR = 3, AR = 4, ARPair = 5, ARPair_with_AROctad_with_OctadHi = 6, AROctad = 7, ARQuad = 8, AR_with_AROctad = 9, ARPair_with_ARQuad = 10, ARPair_with_AROctad = 11, ARQuad_with_AROctad = 12, }; } // end namespace Colossus } // end namespace llvm #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC namespace llvm { extern const int16_t ColossusRegDiffLists[] = { /* 0 */ -8, -84, 0, /* 3 */ -73, 0, /* 5 */ 23, 27, -72, 0, /* 9 */ 24, 27, -72, 0, /* 13 */ 24, 28, -72, 0, /* 17 */ 25, 28, -72, 0, /* 21 */ 22, -45, 0, /* 24 */ 23, -45, 0, /* 27 */ 45, -23, 1, -21, 22, -23, 0, /* 34 */ 25, 28, -16, 0, /* 38 */ 26, 28, -16, 0, /* 42 */ 26, 29, -16, 0, /* 46 */ 27, 29, -16, 0, /* 50 */ 27, 29, -15, 0, /* 54 */ 28, 29, -15, 0, /* 58 */ 28, 30, -15, 0, /* 62 */ 29, 30, -15, 0, /* 66 */ -22, -2, 0, /* 69 */ 1, -2, 0, /* 72 */ -92, -1, 0, /* 75 */ -94, 1, 0, /* 78 */ -29, 1, 0, /* 81 */ -30, -29, 1, 29, -28, 1, 0, /* 88 */ -27, 1, 0, /* 91 */ 15, -30, -29, 1, 29, -28, 1, 57, -29, -27, 1, 27, -26, 1, 0, /* 106 */ -25, 1, 0, /* 109 */ -28, -25, 1, 25, -24, 1, 0, /* 116 */ -23, 1, 0, /* 119 */ -9, 1, 0, /* 122 */ -8, 1, 0, /* 125 */ -4, -8, 1, 8, -7, 1, 0, /* 132 */ -6, 1, 0, /* 135 */ -3, -6, 1, 6, -5, 1, 0, /* 142 */ 1, 1, 1, 1, 1, 1, 1, 0, /* 150 */ 4, 2, 0, /* 153 */ 5, 2, 0, /* 156 */ 5, 3, 0, /* 159 */ 6, 3, 0, /* 162 */ 7, 3, 0, /* 165 */ -93, 4, 0, /* 168 */ 7, 4, 0, /* 171 */ 8, 4, 0, /* 174 */ 5, 0, /* 176 */ 6, 0, /* 178 */ 7, 0, /* 180 */ 8, 0, /* 182 */ 9, 0, /* 184 */ 72, -28, -25, 1, 25, -24, 1, 51, 0, /* 193 */ 59, 0, /* 195 */ 89, 0, /* 197 */ 92, 0, /* 199 */ 93, 0, /* 201 */ 94, 0, }; extern const LaneBitmask ColossusLaneMaskLists[] = { /* 0 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask::getAll(), /* 3 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(), /* 6 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(), /* 11 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000000400), LaneBitmask::getAll(), /* 20 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000F00), LaneBitmask::getAll(), /* 26 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(), }; extern const uint16_t ColossusSubRegIdxLists[] = { /* 0 */ 2, 8, 10, 9, 7, 12, 11, 1, 0, /* 9 */ 10, 9, 0, /* 12 */ 8, 10, 9, 7, 12, 11, 0, /* 19 */ 2, 8, 10, 9, 7, 12, 11, 1, 14, 16, 15, 13, 18, 17, 0, }; #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Woverlength-strings" #endif extern const char ColossusRegStrings[] = { /* 0 */ "A10\0" /* 4 */ "AD10\0" /* 9 */ "AO10\0" /* 14 */ "AQ10\0" /* 19 */ "A0\0" /* 22 */ "ACC0\0" /* 27 */ "AD0\0" /* 31 */ "ACCD0\0" /* 37 */ "MD0\0" /* 41 */ "M0\0" /* 44 */ "AO0\0" /* 48 */ "AQ0\0" /* 52 */ "ACCQ0\0" /* 58 */ "A11\0" /* 62 */ "AD11\0" /* 67 */ "AO11\0" /* 72 */ "AQ11\0" /* 77 */ "A1\0" /* 80 */ "ACC1\0" /* 85 */ "AD1\0" /* 89 */ "ACCD1\0" /* 95 */ "MD1\0" /* 99 */ "M1\0" /* 102 */ "AO1\0" /* 106 */ "AQ1\0" /* 110 */ "ACCQ1\0" /* 116 */ "A12\0" /* 120 */ "AD12\0" /* 125 */ "AO12\0" /* 130 */ "AQ12\0" /* 135 */ "A2\0" /* 138 */ "ACC2\0" /* 143 */ "AD2\0" /* 147 */ "ACCD2\0" /* 153 */ "MD2\0" /* 157 */ "M2\0" /* 160 */ "AO2\0" /* 164 */ "AQ2\0" /* 168 */ "A13\0" /* 172 */ "AD13\0" /* 177 */ "AO13\0" /* 182 */ "AQ13\0" /* 187 */ "A3\0" /* 190 */ "ACC3\0" /* 195 */ "AD3\0" /* 199 */ "ACCD3\0" /* 205 */ "MD3\0" /* 209 */ "M3\0" /* 212 */ "AO3\0" /* 216 */ "AQ3\0" /* 220 */ "A14\0" /* 224 */ "AD14\0" /* 229 */ "M14\0" /* 233 */ "AO14\0" /* 238 */ "AQ14\0" /* 243 */ "A4\0" /* 246 */ "ACC4\0" /* 251 */ "AD4\0" /* 255 */ "MD4\0" /* 259 */ "M4\0" /* 262 */ "AO4\0" /* 266 */ "AQ4\0" /* 270 */ "A5\0" /* 273 */ "ACC5\0" /* 278 */ "AD5\0" /* 282 */ "MD5\0" /* 286 */ "M5\0" /* 289 */ "AO5\0" /* 293 */ "AQ5\0" /* 297 */ "A6\0" /* 300 */ "ACC6\0" /* 305 */ "AD6\0" /* 309 */ "MD6\0" /* 313 */ "M6\0" /* 316 */ "AO6\0" /* 320 */ "AQ6\0" /* 324 */ "A7\0" /* 327 */ "ACC7\0" /* 332 */ "AD7\0" /* 336 */ "MD7\0" /* 340 */ "M7\0" /* 343 */ "AO7\0" /* 347 */ "AQ7\0" /* 351 */ "A8\0" /* 354 */ "AD8\0" /* 358 */ "AO8\0" /* 362 */ "AQ8\0" /* 366 */ "A9\0" /* 369 */ "AD9\0" /* 373 */ "AO9\0" /* 377 */ "AQ9\0" /* 381 */ "MWORKER_BASE\0" /* 394 */ "MVERTEX_BASE\0" /* 407 */ "AZERO\0" /* 413 */ "MZERO\0" /* 419 */ "AOZERO\0" /* 426 */ "AQZERO\0" /* 433 */ "BP\0" /* 436 */ "FP\0" /* 439 */ "SP\0" /* 442 */ "LR\0" /* 445 */ "AZEROS\0" }; #ifdef __GNUC__ #pragma GCC diagnostic pop #endif extern const MCRegisterDesc ColossusRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0, 0, 0 }, { 419, 184, 2, 0, 593920, 20, 0, 0 }, { 426, 27, 2, 12, 598021, 6, 1, 0 }, { 407, 2, 69, 8, 8200, 26, 1, 0 }, { 445, 31, 67, 9, 311303, 0, 1, 0 }, { 433, 2, 201, 8, 8201, 26, 0, 0 }, { 436, 2, 199, 8, 8202, 26, 0, 0 }, { 442, 2, 199, 8, 8203, 26, 0, 0 }, { 394, 2, 199, 8, 8204, 26, 0, 0 }, { 381, 2, 197, 8, 8205, 26, 0, 0 }, { 413, 2, 197, 8, 8206, 26, 1, 0 }, { 439, 2, 195, 8, 8207, 26, 0, 0 }, { 19, 2, 62, 8, 8208, 26, 0, 0 }, { 77, 2, 58, 8, 8209, 26, 0, 0 }, { 135, 2, 54, 8, 8210, 26, 0, 0 }, { 187, 2, 50, 8, 8211, 26, 0, 0 }, { 243, 2, 46, 8, 8212, 26, 0, 0 }, { 270, 2, 42, 8, 8213, 26, 0, 0 }, { 297, 2, 38, 8, 8214, 26, 0, 0 }, { 324, 2, 34, 8, 8215, 26, 0, 0 }, { 351, 2, 17, 8, 8192, 26, 0, 0 }, { 366, 2, 13, 8, 8193, 26, 0, 0 }, { 0, 2, 9, 8, 8194, 26, 0, 0 }, { 58, 2, 5, 8, 8195, 26, 0, 0 }, { 116, 2, 24, 8, 8197, 26, 0, 0 }, { 168, 2, 21, 8, 8198, 26, 0, 0 }, { 220, 2, 66, 8, 8199, 26, 0, 0 }, { 22, 2, 171, 8, 8216, 26, 0, 0 }, { 80, 2, 168, 8, 8217, 26, 0, 0 }, { 138, 2, 162, 8, 8218, 26, 0, 0 }, { 190, 2, 159, 8, 8219, 26, 0, 0 }, { 246, 2, 159, 8, 8220, 26, 0, 0 }, { 273, 2, 156, 8, 8221, 26, 0, 0 }, { 300, 2, 153, 8, 8222, 26, 0, 0 }, { 327, 2, 150, 8, 8223, 26, 0, 0 }, { 31, 122, 166, 9, 311320, 0, 0, 0 }, { 89, 129, 157, 9, 311322, 0, 0, 0 }, { 147, 132, 157, 9, 311324, 0, 0, 0 }, { 199, 139, 151, 9, 311326, 0, 0, 0 }, { 52, 125, 2, 12, 598040, 6, 0, 0 }, { 110, 135, 2, 12, 598044, 6, 0, 0 }, { 27, 78, 59, 9, 311312, 0, 0, 0 }, { 85, 85, 51, 9, 311314, 0, 0, 0 }, { 143, 88, 43, 9, 311316, 0, 0, 0 }, { 195, 103, 35, 9, 311318, 0, 0, 0 }, { 251, 106, 14, 9, 311296, 0, 0, 0 }, { 278, 113, 6, 9, 311298, 0, 0, 0 }, { 305, 116, 22, 9, 311301, 0, 0, 0 }, { 332, 2, 2, 8, 8224, 26, 0, 0 }, { 354, 2, 2, 8, 8225, 26, 0, 0 }, { 369, 2, 2, 8, 8226, 26, 0, 0 }, { 4, 2, 2, 8, 8227, 26, 0, 0 }, { 62, 2, 2, 8, 8228, 26, 0, 0 }, { 120, 2, 2, 8, 8229, 26, 0, 0 }, { 172, 2, 2, 8, 8230, 26, 0, 0 }, { 224, 2, 2, 8, 8231, 26, 0, 0 }, { 44, 91, 2, 19, 581648, 11, 0, 0 }, { 102, 2, 2, 8, 8232, 26, 0, 0 }, { 160, 2, 2, 8, 8233, 26, 0, 0 }, { 212, 2, 2, 8, 8234, 26, 0, 0 }, { 262, 2, 2, 8, 8235, 26, 0, 0 }, { 289, 2, 2, 8, 8236, 26, 0, 0 }, { 316, 2, 2, 8, 8237, 26, 0, 0 }, { 343, 2, 2, 8, 8238, 26, 0, 0 }, { 358, 2, 2, 8, 8239, 26, 0, 0 }, { 373, 2, 2, 8, 8240, 26, 0, 0 }, { 9, 2, 2, 8, 8241, 26, 0, 0 }, { 67, 2, 2, 8, 8242, 26, 0, 0 }, { 125, 2, 2, 8, 8243, 26, 0, 0 }, { 177, 2, 2, 8, 8244, 26, 0, 0 }, { 233, 2, 2, 8, 8245, 26, 0, 0 }, { 48, 81, 52, 12, 598032, 6, 0, 0 }, { 106, 99, 36, 12, 598036, 6, 0, 0 }, { 164, 109, 7, 12, 598016, 6, 0, 0 }, { 216, 2, 3, 8, 8196, 26, 0, 0 }, { 266, 2, 2, 8, 8246, 26, 0, 0 }, { 293, 2, 2, 8, 8247, 26, 0, 0 }, { 320, 2, 2, 8, 8248, 26, 0, 0 }, { 347, 2, 2, 8, 8249, 26, 0, 0 }, { 362, 2, 2, 8, 8250, 26, 0, 0 }, { 377, 2, 2, 8, 8251, 26, 0, 0 }, { 14, 2, 2, 8, 8252, 26, 0, 0 }, { 72, 2, 2, 8, 8253, 26, 0, 0 }, { 130, 2, 2, 8, 8254, 26, 0, 0 }, { 182, 2, 2, 8, 8255, 26, 0, 0 }, { 238, 2, 2, 8, 8256, 26, 0, 0 }, { 41, 2, 182, 8, 8257, 26, 0, 0 }, { 99, 2, 180, 8, 8258, 26, 0, 0 }, { 157, 2, 180, 8, 8259, 26, 0, 0 }, { 209, 2, 178, 8, 8260, 26, 0, 0 }, { 259, 2, 178, 8, 8261, 26, 0, 0 }, { 286, 2, 176, 8, 8262, 26, 0, 0 }, { 313, 2, 176, 8, 8263, 26, 0, 0 }, { 340, 2, 174, 8, 8264, 26, 0, 0 }, { 229, 2, 180, 8, 8265, 26, 0, 0 }, { 37, 119, 2, 9, 311361, 0, 0, 0 }, { 95, 122, 2, 9, 311363, 0, 0, 0 }, { 153, 129, 2, 9, 311365, 0, 0, 0 }, { 205, 132, 2, 9, 311367, 0, 0, 0 }, { 255, 75, 2, 9, 311305, 0, 0, 0 }, { 282, 165, 2, 9, 679947, 0, 0, 0 }, { 309, 72, 2, 9, 311308, 3, 0, 0 }, { 336, 0, 2, 9, 790542, 3, 0, 0 }, }; extern const MCPhysReg ColossusRegUnitRoots[][2] = { { Colossus::A8 }, { Colossus::A9 }, { Colossus::A10 }, { Colossus::A11 }, { Colossus::AQ3 }, { Colossus::A12 }, { Colossus::A13 }, { Colossus::A14 }, { Colossus::AZERO }, { Colossus::BP }, { Colossus::FP }, { Colossus::LR }, { Colossus::MVERTEX_BASE }, { Colossus::MWORKER_BASE }, { Colossus::MZERO }, { Colossus::SP }, { Colossus::A0 }, { Colossus::A1 }, { Colossus::A2 }, { Colossus::A3 }, { Colossus::A4 }, { Colossus::A5 }, { Colossus::A6 }, { Colossus::A7 }, { Colossus::ACC0 }, { Colossus::ACC1 }, { Colossus::ACC2 }, { Colossus::ACC3 }, { Colossus::ACC4 }, { Colossus::ACC5 }, { Colossus::ACC6 }, { Colossus::ACC7 }, { Colossus::AD7 }, { Colossus::AD8 }, { Colossus::AD9 }, { Colossus::AD10 }, { Colossus::AD11 }, { Colossus::AD12 }, { Colossus::AD13 }, { Colossus::AD14 }, { Colossus::AO1 }, { Colossus::AO2 }, { Colossus::AO3 }, { Colossus::AO4 }, { Colossus::AO5 }, { Colossus::AO6 }, { Colossus::AO7 }, { Colossus::AO8 }, { Colossus::AO9 }, { Colossus::AO10 }, { Colossus::AO11 }, { Colossus::AO12 }, { Colossus::AO13 }, { Colossus::AO14 }, { Colossus::AQ4 }, { Colossus::AQ5 }, { Colossus::AQ6 }, { Colossus::AQ7 }, { Colossus::AQ8 }, { Colossus::AQ9 }, { Colossus::AQ10 }, { Colossus::AQ11 }, { Colossus::AQ12 }, { Colossus::AQ13 }, { Colossus::AQ14 }, { Colossus::M0 }, { Colossus::M1 }, { Colossus::M2 }, { Colossus::M3 }, { Colossus::M4 }, { Colossus::M5 }, { Colossus::M6 }, { Colossus::M7 }, { Colossus::M14 }, }; namespace { // Register classes... // AR Register Class... const MCPhysReg AR[] = { Colossus::A0, Colossus::A1, Colossus::A2, Colossus::A3, Colossus::A4, Colossus::A5, Colossus::A6, Colossus::A7, Colossus::A8, Colossus::A9, Colossus::A10, Colossus::A11, Colossus::A12, Colossus::A13, Colossus::A14, Colossus::AZERO, }; // AR Bit set. const uint8_t ARBits[] = { 0x08, 0xf0, 0xff, 0x07, }; // MR Register Class... const MCPhysReg MR[] = { Colossus::M0, Colossus::M1, Colossus::M2, Colossus::M3, Colossus::M4, Colossus::M5, Colossus::M6, Colossus::M7, Colossus::BP, Colossus::FP, Colossus::LR, Colossus::SP, Colossus::MWORKER_BASE, Colossus::MVERTEX_BASE, Colossus::M14, Colossus::MZERO, }; // MR Bit set. const uint8_t MRBits[] = { 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, }; // ACC Register Class... const MCPhysReg ACC[] = { Colossus::ACC0, Colossus::ACC1, Colossus::ACC2, Colossus::ACC3, Colossus::ACC4, Colossus::ACC5, Colossus::ACC6, Colossus::ACC7, }; // ACC Bit set. const uint8_t ACCBits[] = { 0x00, 0x00, 0x00, 0xf8, 0x07, }; // ARPair Register Class... const MCPhysReg ARPair[] = { Colossus::AD0, Colossus::AD1, Colossus::AD2, Colossus::AD3, Colossus::AD4, Colossus::AD5, Colossus::AD6, Colossus::AD7, Colossus::AD8, Colossus::AD9, Colossus::AD10, Colossus::AD11, Colossus::AD12, Colossus::AD13, Colossus::AD14, Colossus::AZEROS, }; // ARPair Bit set. const uint8_t ARPairBits[] = { 0x10, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, }; // ARPair_with_SubRegHi Register Class... const MCPhysReg ARPair_with_SubRegHi[] = { Colossus::AD0, Colossus::AD1, Colossus::AD2, Colossus::AD3, Colossus::AD4, Colossus::AD5, Colossus::AD6, Colossus::AZEROS, }; // ARPair_with_SubRegHi Bit set. const uint8_t ARPair_with_SubRegHiBits[] = { 0x10, 0x00, 0x00, 0x00, 0x00, 0xfe, }; // MRPair Register Class... const MCPhysReg MRPair[] = { Colossus::MD0, Colossus::MD1, Colossus::MD2, Colossus::MD3, Colossus::MD4, Colossus::MD5, Colossus::MD6, Colossus::MD7, }; // MRPair Bit set. const uint8_t MRPairBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, }; // ACCPair Register Class... const MCPhysReg ACCPair[] = { Colossus::ACCD0, Colossus::ACCD1, Colossus::ACCD2, Colossus::ACCD3, }; // ACCPair Bit set. const uint8_t ACCPairBits[] = { 0x00, 0x00, 0x00, 0x00, 0x78, }; // ARQuad Register Class... const MCPhysReg ARQuad[] = { Colossus::AQ0, Colossus::AQ1, Colossus::AQ2, Colossus::AQ3, Colossus::AQ4, Colossus::AQ5, Colossus::AQ6, Colossus::AQ7, Colossus::AQ8, Colossus::AQ9, Colossus::AQ10, Colossus::AQ11, Colossus::AQ12, Colossus::AQ13, Colossus::AQ14, Colossus::AQZERO, }; // ARQuad Bit set. const uint8_t ARQuadBits[] = { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, }; // ARQuad_with_QuadHi Register Class... const MCPhysReg ARQuad_with_QuadHi[] = { Colossus::AQ0, Colossus::AQ1, Colossus::AQ2, Colossus::AQZERO, }; // ARQuad_with_QuadHi Bit set. const uint8_t ARQuad_with_QuadHiBits[] = { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, }; // ACCQuad Register Class... const MCPhysReg ACCQuad[] = { Colossus::ACCQ0, Colossus::ACCQ1, }; // ACCQuad Bit set. const uint8_t ACCQuadBits[] = { 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, }; // AROctad Register Class... const MCPhysReg AROctad[] = { Colossus::AO0, Colossus::AO1, Colossus::AO2, Colossus::AO3, Colossus::AO4, Colossus::AO5, Colossus::AO6, Colossus::AO7, Colossus::AO8, Colossus::AO9, Colossus::AO10, Colossus::AO11, Colossus::AO12, Colossus::AO13, Colossus::AO14, Colossus::AOZERO, }; // AROctad Bit set. const uint8_t AROctadBits[] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, }; // AROctad_with_OctadHi Register Class... const MCPhysReg AROctad_with_OctadHi[] = { Colossus::AO0, Colossus::AOZERO, }; // AROctad_with_OctadHi Bit set. const uint8_t AROctad_with_OctadHiBits[] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, }; // AROctad_with_OctadHi_then_QuadHi Register Class... const MCPhysReg AROctad_with_OctadHi_then_QuadHi[] = { Colossus::AO0, }; // AROctad_with_OctadHi_then_QuadHi Bit set. const uint8_t AROctad_with_OctadHi_then_QuadHiBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, }; } // end anonymous namespace #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Woverlength-strings" #endif extern const char ColossusRegClassStrings[] = { /* 0 */ "ACC\0" /* 4 */ "AR\0" /* 7 */ "MR\0" /* 10 */ "AROctad\0" /* 18 */ "ACCQuad\0" /* 26 */ "ARQuad\0" /* 33 */ "AROctad_with_OctadHi\0" /* 54 */ "ARQuad_with_QuadHi\0" /* 73 */ "AROctad_with_OctadHi_then_QuadHi\0" /* 106 */ "ARPair_with_SubRegHi\0" /* 127 */ "ACCPair\0" /* 135 */ "ARPair\0" /* 142 */ "MRPair\0" }; #ifdef __GNUC__ #pragma GCC diagnostic pop #endif extern const MCRegisterClass ColossusMCRegisterClasses[] = { { AR, ARBits, 4, 16, sizeof(ARBits), Colossus::ARRegClassID, 32, 1, true, false }, { MR, MRBits, 7, 16, sizeof(MRBits), Colossus::MRRegClassID, 32, 1, true, false }, { ACC, ACCBits, 0, 8, sizeof(ACCBits), Colossus::ACCRegClassID, 32, 1, true, false }, { ARPair, ARPairBits, 135, 16, sizeof(ARPairBits), Colossus::ARPairRegClassID, 64, 1, true, false }, { ARPair_with_SubRegHi, ARPair_with_SubRegHiBits, 106, 8, sizeof(ARPair_with_SubRegHiBits), Colossus::ARPair_with_SubRegHiRegClassID, 64, 1, true, false }, { MRPair, MRPairBits, 142, 8, sizeof(MRPairBits), Colossus::MRPairRegClassID, 64, 1, true, false }, { ACCPair, ACCPairBits, 127, 4, sizeof(ACCPairBits), Colossus::ACCPairRegClassID, 64, 1, true, false }, { ARQuad, ARQuadBits, 26, 16, sizeof(ARQuadBits), Colossus::ARQuadRegClassID, 128, 1, true, false }, { ARQuad_with_QuadHi, ARQuad_with_QuadHiBits, 54, 4, sizeof(ARQuad_with_QuadHiBits), Colossus::ARQuad_with_QuadHiRegClassID, 128, 1, true, false }, { ACCQuad, ACCQuadBits, 18, 2, sizeof(ACCQuadBits), Colossus::ACCQuadRegClassID, 128, 1, true, false }, { AROctad, AROctadBits, 10, 16, sizeof(AROctadBits), Colossus::AROctadRegClassID, 256, 1, true, false }, { AROctad_with_OctadHi, AROctad_with_OctadHiBits, 33, 2, sizeof(AROctad_with_OctadHiBits), Colossus::AROctad_with_OctadHiRegClassID, 256, 1, true, false }, { AROctad_with_OctadHi_then_QuadHi, AROctad_with_OctadHi_then_QuadHiBits, 73, 1, sizeof(AROctad_with_OctadHi_then_QuadHiBits), Colossus::AROctad_with_OctadHi_then_QuadHiRegClassID, 256, 1, true, false }, }; // Colossus Dwarf<->LLVM register mappings. extern const MCRegisterInfo::DwarfLLVMRegPair ColossusDwarfFlavour0Dwarf2L[] = { { 0U, Colossus::M0 }, { 1U, Colossus::M1 }, { 2U, Colossus::M2 }, { 3U, Colossus::M3 }, { 4U, Colossus::M4 }, { 5U, Colossus::M5 }, { 6U, Colossus::M6 }, { 7U, Colossus::M7 }, { 8U, Colossus::BP }, { 9U, Colossus::FP }, { 10U, Colossus::LR }, { 11U, Colossus::SP }, { 12U, Colossus::MWORKER_BASE }, { 13U, Colossus::MVERTEX_BASE }, { 14U, Colossus::M14 }, { 15U, Colossus::A0 }, { 16U, Colossus::A1 }, { 17U, Colossus::A2 }, { 18U, Colossus::A3 }, { 19U, Colossus::A4 }, { 20U, Colossus::A5 }, { 21U, Colossus::A6 }, { 22U, Colossus::A7 }, { 23U, Colossus::A8 }, { 24U, Colossus::A9 }, { 25U, Colossus::A10 }, { 26U, Colossus::A11 }, { 27U, Colossus::A12 }, { 28U, Colossus::A13 }, { 29U, Colossus::A14 }, { 31U, Colossus::AZERO }, { 32U, Colossus::MD0 }, { 33U, Colossus::MD1 }, { 34U, Colossus::MD2 }, { 35U, Colossus::MD3 }, { 36U, Colossus::MD4 }, { 37U, Colossus::MD5 }, { 38U, Colossus::MD6 }, { 39U, Colossus::MD7 }, { 40U, Colossus::AD0 }, { 41U, Colossus::AD1 }, { 42U, Colossus::AD2 }, { 43U, Colossus::AD3 }, { 44U, Colossus::AD4 }, { 45U, Colossus::AD5 }, { 46U, Colossus::AD6 }, { 47U, Colossus::AZEROS }, { 48U, Colossus::AQ0 }, { 49U, Colossus::AQ1 }, { 50U, Colossus::AQ2 }, { 51U, Colossus::AQZERO }, { 52U, Colossus::ACC0 }, { 53U, Colossus::ACC1 }, { 54U, Colossus::ACC2 }, { 55U, Colossus::ACC3 }, { 56U, Colossus::ACC4 }, { 57U, Colossus::ACC5 }, { 58U, Colossus::ACC6 }, { 59U, Colossus::ACC7 }, { 60U, Colossus::ACCD0 }, { 61U, Colossus::ACCD1 }, { 62U, Colossus::ACCD2 }, { 63U, Colossus::ACCD3 }, { 64U, Colossus::ACCQ0 }, { 65U, Colossus::ACCQ1 }, { 73U, Colossus::AD7 }, { 74U, Colossus::AD8 }, { 75U, Colossus::AD9 }, { 76U, Colossus::AO0 }, { 77U, Colossus::AD11 }, { 78U, Colossus::AQ3 }, { 79U, Colossus::AQ4 }, { 80U, Colossus::AQ5 }, { 81U, Colossus::AQ6 }, { 82U, Colossus::AQ7 }, { 83U, Colossus::AQ8 }, { 84U, Colossus::AQ9 }, { 85U, Colossus::AQ10 }, { 86U, Colossus::AQ11 }, { 87U, Colossus::AQ12 }, { 88U, Colossus::AQ13 }, { 89U, Colossus::AQ14 }, { 90U, Colossus::AO12 }, { 91U, Colossus::AO13 }, { 92U, Colossus::AO14 }, }; extern const unsigned ColossusDwarfFlavour0Dwarf2LSize = std::size(ColossusDwarfFlavour0Dwarf2L); extern const MCRegisterInfo::DwarfLLVMRegPair ColossusEHFlavour0Dwarf2L[] = { { 0U, Colossus::M0 }, { 1U, Colossus::M1 }, { 2U, Colossus::M2 }, { 3U, Colossus::M3 }, { 4U, Colossus::M4 }, { 5U, Colossus::M5 }, { 6U, Colossus::M6 }, { 7U, Colossus::M7 }, { 8U, Colossus::BP }, { 9U, Colossus::FP }, { 10U, Colossus::LR }, { 11U, Colossus::SP }, { 12U, Colossus::MWORKER_BASE }, { 13U, Colossus::MVERTEX_BASE }, { 14U, Colossus::M14 }, { 15U, Colossus::A0 }, { 16U, Colossus::A1 }, { 17U, Colossus::A2 }, { 18U, Colossus::A3 }, { 19U, Colossus::A4 }, { 20U, Colossus::A5 }, { 21U, Colossus::A6 }, { 22U, Colossus::A7 }, { 23U, Colossus::A8 }, { 24U, Colossus::A9 }, { 25U, Colossus::A10 }, { 26U, Colossus::A11 }, { 27U, Colossus::A12 }, { 28U, Colossus::A13 }, { 29U, Colossus::A14 }, { 31U, Colossus::AZERO }, { 32U, Colossus::MD0 }, { 33U, Colossus::MD1 }, { 34U, Colossus::MD2 }, { 35U, Colossus::MD3 }, { 36U, Colossus::MD4 }, { 37U, Colossus::MD5 }, { 38U, Colossus::MD6 }, { 39U, Colossus::MD7 }, { 40U, Colossus::AD0 }, { 41U, Colossus::AD1 }, { 42U, Colossus::AD2 }, { 43U, Colossus::AD3 }, { 44U, Colossus::AD4 }, { 45U, Colossus::AD5 }, { 46U, Colossus::AD6 }, { 47U, Colossus::AZEROS }, { 48U, Colossus::AQ0 }, { 49U, Colossus::AQ1 }, { 50U, Colossus::AQ2 }, { 51U, Colossus::AQZERO }, { 52U, Colossus::ACC0 }, { 53U, Colossus::ACC1 }, { 54U, Colossus::ACC2 }, { 55U, Colossus::ACC3 }, { 56U, Colossus::ACC4 }, { 57U, Colossus::ACC5 }, { 58U, Colossus::ACC6 }, { 59U, Colossus::ACC7 }, { 60U, Colossus::ACCD0 }, { 61U, Colossus::ACCD1 }, { 62U, Colossus::ACCD2 }, { 63U, Colossus::ACCD3 }, { 64U, Colossus::ACCQ0 }, { 65U, Colossus::ACCQ1 }, { 73U, Colossus::AD7 }, { 74U, Colossus::AD8 }, { 75U, Colossus::AD9 }, { 76U, Colossus::AO0 }, { 77U, Colossus::AD11 }, { 78U, Colossus::AQ3 }, { 79U, Colossus::AQ4 }, { 80U, Colossus::AQ5 }, { 81U, Colossus::AQ6 }, { 82U, Colossus::AQ7 }, { 83U, Colossus::AQ8 }, { 84U, Colossus::AQ9 }, { 85U, Colossus::AQ10 }, { 86U, Colossus::AQ11 }, { 87U, Colossus::AQ12 }, { 88U, Colossus::AQ13 }, { 89U, Colossus::AQ14 }, { 90U, Colossus::AO12 }, { 91U, Colossus::AO13 }, { 92U, Colossus::AO14 }, }; extern const unsigned ColossusEHFlavour0Dwarf2LSize = std::size(ColossusEHFlavour0Dwarf2L); extern const MCRegisterInfo::DwarfLLVMRegPair ColossusDwarfFlavour0L2Dwarf[] = { { Colossus::AOZERO, 77U }, { Colossus::AQZERO, 51U }, { Colossus::AZERO, 31U }, { Colossus::AZEROS, 47U }, { Colossus::BP, 8U }, { Colossus::FP, 9U }, { Colossus::LR, 10U }, { Colossus::MVERTEX_BASE, 13U }, { Colossus::MWORKER_BASE, 12U }, { Colossus::MZERO, 15U }, { Colossus::SP, 11U }, { Colossus::A0, 15U }, { Colossus::A1, 16U }, { Colossus::A2, 17U }, { Colossus::A3, 18U }, { Colossus::A4, 19U }, { Colossus::A5, 20U }, { Colossus::A6, 21U }, { Colossus::A7, 22U }, { Colossus::A8, 23U }, { Colossus::A9, 24U }, { Colossus::A10, 25U }, { Colossus::A11, 26U }, { Colossus::A12, 27U }, { Colossus::A13, 28U }, { Colossus::A14, 29U }, { Colossus::ACC0, 52U }, { Colossus::ACC1, 53U }, { Colossus::ACC2, 54U }, { Colossus::ACC3, 55U }, { Colossus::ACC4, 56U }, { Colossus::ACC5, 57U }, { Colossus::ACC6, 58U }, { Colossus::ACC7, 59U }, { Colossus::ACCD0, 60U }, { Colossus::ACCD1, 61U }, { Colossus::ACCD2, 62U }, { Colossus::ACCD3, 63U }, { Colossus::ACCQ0, 64U }, { Colossus::ACCQ1, 65U }, { Colossus::AD0, 40U }, { Colossus::AD1, 41U }, { Colossus::AD2, 42U }, { Colossus::AD3, 43U }, { Colossus::AD4, 44U }, { Colossus::AD5, 45U }, { Colossus::AD6, 46U }, { Colossus::AD7, 73U }, { Colossus::AD8, 74U }, { Colossus::AD9, 75U }, { Colossus::AD10, 76U }, { Colossus::AD11, 77U }, { Colossus::AD12, 78U }, { Colossus::AD13, 79U }, { Colossus::AD14, 80U }, { Colossus::AO0, 76U }, { Colossus::AO1, 79U }, { Colossus::AO2, 80U }, { Colossus::AO3, 81U }, { Colossus::AO4, 82U }, { Colossus::AO5, 83U }, { Colossus::AO6, 84U }, { Colossus::AO7, 85U }, { Colossus::AO8, 86U }, { Colossus::AO9, 87U }, { Colossus::AO10, 88U }, { Colossus::AO11, 89U }, { Colossus::AO12, 90U }, { Colossus::AO13, 91U }, { Colossus::AO14, 92U }, { Colossus::AQ0, 48U }, { Colossus::AQ1, 49U }, { Colossus::AQ2, 50U }, { Colossus::AQ3, 78U }, { Colossus::AQ4, 79U }, { Colossus::AQ5, 80U }, { Colossus::AQ6, 81U }, { Colossus::AQ7, 82U }, { Colossus::AQ8, 83U }, { Colossus::AQ9, 84U }, { Colossus::AQ10, 85U }, { Colossus::AQ11, 86U }, { Colossus::AQ12, 87U }, { Colossus::AQ13, 88U }, { Colossus::AQ14, 89U }, { Colossus::M0, 0U }, { Colossus::M1, 1U }, { Colossus::M2, 2U }, { Colossus::M3, 3U }, { Colossus::M4, 4U }, { Colossus::M5, 5U }, { Colossus::M6, 6U }, { Colossus::M7, 7U }, { Colossus::M14, 14U }, { Colossus::MD0, 32U }, { Colossus::MD1, 33U }, { Colossus::MD2, 34U }, { Colossus::MD3, 35U }, { Colossus::MD4, 36U }, { Colossus::MD5, 37U }, { Colossus::MD6, 38U }, { Colossus::MD7, 39U }, }; extern const unsigned ColossusDwarfFlavour0L2DwarfSize = std::size(ColossusDwarfFlavour0L2Dwarf); extern const MCRegisterInfo::DwarfLLVMRegPair ColossusEHFlavour0L2Dwarf[] = { { Colossus::AOZERO, 77U }, { Colossus::AQZERO, 51U }, { Colossus::AZERO, 31U }, { Colossus::AZEROS, 47U }, { Colossus::BP, 8U }, { Colossus::FP, 9U }, { Colossus::LR, 10U }, { Colossus::MVERTEX_BASE, 13U }, { Colossus::MWORKER_BASE, 12U }, { Colossus::MZERO, 15U }, { Colossus::SP, 11U }, { Colossus::A0, 15U }, { Colossus::A1, 16U }, { Colossus::A2, 17U }, { Colossus::A3, 18U }, { Colossus::A4, 19U }, { Colossus::A5, 20U }, { Colossus::A6, 21U }, { Colossus::A7, 22U }, { Colossus::A8, 23U }, { Colossus::A9, 24U }, { Colossus::A10, 25U }, { Colossus::A11, 26U }, { Colossus::A12, 27U }, { Colossus::A13, 28U }, { Colossus::A14, 29U }, { Colossus::ACC0, 52U }, { Colossus::ACC1, 53U }, { Colossus::ACC2, 54U }, { Colossus::ACC3, 55U }, { Colossus::ACC4, 56U }, { Colossus::ACC5, 57U }, { Colossus::ACC6, 58U }, { Colossus::ACC7, 59U }, { Colossus::ACCD0, 60U }, { Colossus::ACCD1, 61U }, { Colossus::ACCD2, 62U }, { Colossus::ACCD3, 63U }, { Colossus::ACCQ0, 64U }, { Colossus::ACCQ1, 65U }, { Colossus::AD0, 40U }, { Colossus::AD1, 41U }, { Colossus::AD2, 42U }, { Colossus::AD3, 43U }, { Colossus::AD4, 44U }, { Colossus::AD5, 45U }, { Colossus::AD6, 46U }, { Colossus::AD7, 73U }, { Colossus::AD8, 74U }, { Colossus::AD9, 75U }, { Colossus::AD10, 76U }, { Colossus::AD11, 77U }, { Colossus::AD12, 78U }, { Colossus::AD13, 79U }, { Colossus::AD14, 80U }, { Colossus::AO0, 76U }, { Colossus::AO1, 79U }, { Colossus::AO2, 80U }, { Colossus::AO3, 81U }, { Colossus::AO4, 82U }, { Colossus::AO5, 83U }, { Colossus::AO6, 84U }, { Colossus::AO7, 85U }, { Colossus::AO8, 86U }, { Colossus::AO9, 87U }, { Colossus::AO10, 88U }, { Colossus::AO11, 89U }, { Colossus::AO12, 90U }, { Colossus::AO13, 91U }, { Colossus::AO14, 92U }, { Colossus::AQ0, 48U }, { Colossus::AQ1, 49U }, { Colossus::AQ2, 50U }, { Colossus::AQ3, 78U }, { Colossus::AQ4, 79U }, { Colossus::AQ5, 80U }, { Colossus::AQ6, 81U }, { Colossus::AQ7, 82U }, { Colossus::AQ8, 83U }, { Colossus::AQ9, 84U }, { Colossus::AQ10, 85U }, { Colossus::AQ11, 86U }, { Colossus::AQ12, 87U }, { Colossus::AQ13, 88U }, { Colossus::AQ14, 89U }, { Colossus::M0, 0U }, { Colossus::M1, 1U }, { Colossus::M2, 2U }, { Colossus::M3, 3U }, { Colossus::M4, 4U }, { Colossus::M5, 5U }, { Colossus::M6, 6U }, { Colossus::M7, 7U }, { Colossus::M14, 14U }, { Colossus::MD0, 32U }, { Colossus::MD1, 33U }, { Colossus::MD2, 34U }, { Colossus::MD3, 35U }, { Colossus::MD4, 36U }, { Colossus::MD5, 37U }, { Colossus::MD6, 38U }, { Colossus::MD7, 39U }, }; extern const unsigned ColossusEHFlavour0L2DwarfSize = std::size(ColossusEHFlavour0L2Dwarf); extern const uint16_t ColossusRegEncodingTable[] = { 0, 4, 15, 15, 15, 8, 9, 10, 13, 12, 15, 11, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 1, 2, 3, 4, 5, 6, 7, 0, 2, 4, 6, 0, 4, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0, 1, 2, 3, 4, 5, 6, 7, 14, 0, 2, 4, 6, 8, 10, 12, 14, }; static inline void InitColossusMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { RI->InitMCRegisterInfo(ColossusRegDesc, 103, RA, PC, ColossusMCRegisterClasses, 13, ColossusRegUnitRoots, 74, ColossusRegDiffLists, ColossusLaneMaskLists, ColossusRegStrings, ColossusRegClassStrings, ColossusSubRegIdxLists, 19, ColossusRegEncodingTable); switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapDwarfRegsToLLVMRegs(ColossusDwarfFlavour0Dwarf2L, ColossusDwarfFlavour0Dwarf2LSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapDwarfRegsToLLVMRegs(ColossusEHFlavour0Dwarf2L, ColossusEHFlavour0Dwarf2LSize, true); break; } switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapLLVMRegsToDwarfRegs(ColossusDwarfFlavour0L2Dwarf, ColossusDwarfFlavour0L2DwarfSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapLLVMRegsToDwarfRegs(ColossusEHFlavour0L2Dwarf, ColossusEHFlavour0L2DwarfSize, true); break; } } } // end namespace llvm #endif // GET_REGINFO_MC_DESC /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Register Information Header Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_HEADER #undef GET_REGINFO_HEADER #include "llvm/CodeGen/TargetRegisterInfo.h" namespace llvm { class ColossusFrameLowering; struct ColossusGenRegisterInfo : public TargetRegisterInfo { explicit ColossusGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0, unsigned HwMode = 0); unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override; const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override; const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; unsigned getRegUnitWeight(unsigned RegUnit) const override; unsigned getNumRegPressureSets() const override; const char *getRegPressureSetName(unsigned Idx) const override; unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; const int *getRegUnitPressureSets(unsigned RegUnit) const override; ArrayRef getRegMaskNames() const override; ArrayRef getRegMasks() const override; bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override; bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override; bool isFixedRegister(const MachineFunction &, MCRegister) const override; bool isArgumentRegister(const MachineFunction &, MCRegister) const override; bool isConstantPhysReg(MCRegister PhysReg) const override final; /// Devirtualized TargetFrameLowering. static const ColossusFrameLowering *getFrameLowering( const MachineFunction &MF); }; namespace Colossus { // Register classes extern const TargetRegisterClass ARRegClass; extern const TargetRegisterClass MRRegClass; extern const TargetRegisterClass ACCRegClass; extern const TargetRegisterClass ARPairRegClass; extern const TargetRegisterClass ARPair_with_SubRegHiRegClass; extern const TargetRegisterClass MRPairRegClass; extern const TargetRegisterClass ACCPairRegClass; extern const TargetRegisterClass ARQuadRegClass; extern const TargetRegisterClass ARQuad_with_QuadHiRegClass; extern const TargetRegisterClass ACCQuadRegClass; extern const TargetRegisterClass AROctadRegClass; extern const TargetRegisterClass AROctad_with_OctadHiRegClass; extern const TargetRegisterClass AROctad_with_OctadHi_then_QuadHiRegClass; } // end namespace Colossus } // end namespace llvm #endif // GET_REGINFO_HEADER /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register and Register Classes Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_TARGET_DESC #undef GET_REGINFO_TARGET_DESC namespace llvm { extern const MCRegisterClass ColossusMCRegisterClasses[]; static const MVT::SimpleValueType VTLists[] = { /* 0 */ MVT::f32, MVT::Other, /* 2 */ MVT::i32, MVT::v2i16, MVT::Other, /* 5 */ MVT::v2i32, MVT::v4i16, MVT::Other, /* 8 */ MVT::f32, MVT::f16, MVT::v2f16, MVT::Other, /* 12 */ MVT::v2f32, MVT::v4f16, MVT::Other, /* 15 */ MVT::v2f32, MVT::Other, /* 17 */ MVT::v4f32, MVT::Other, /* 19 */ MVT::v8f32, MVT::Other, }; static const char *SubRegIndexNameTable[] = { "OctadHi", "OctadLo", "QuadAR0", "QuadAR1", "QuadAR2", "QuadAR3", "QuadHi", "QuadLo", "SubRegHi", "SubRegLo", "QuadHi_then_SubRegHi", "QuadHi_then_SubRegLo", "OctadHi_then_QuadHi", "OctadHi_then_QuadLo", "OctadHi_then_SubRegHi", "OctadHi_then_SubRegLo", "OctadHi_then_QuadHi_then_SubRegHi", "OctadHi_then_QuadHi_then_SubRegLo", "" }; static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = { { 65535, 65535 }, { 128, 128 }, // OctadHi { 0, 128 }, // OctadLo { 0, 32 }, // QuadAR0 { 32, 32 }, // QuadAR1 { 64, 32 }, // QuadAR2 { 96, 32 }, // QuadAR3 { 64, 64 }, // QuadHi { 0, 64 }, // QuadLo { 32, 32 }, // SubRegHi { 0, 32 }, // SubRegLo { 96, 32 }, // QuadHi_then_SubRegHi { 64, 32 }, // QuadHi_then_SubRegLo { 192, 64 }, // OctadHi_then_QuadHi { 128, 64 }, // OctadHi_then_QuadLo { 160, 32 }, // OctadHi_then_SubRegHi { 128, 32 }, // OctadHi_then_SubRegLo { 224, 32 }, // OctadHi_then_QuadHi_then_SubRegHi { 192, 32 }, // OctadHi_then_QuadHi_then_SubRegLo }; static const LaneBitmask SubRegIndexLaneMaskTable[] = { LaneBitmask::getAll(), LaneBitmask(0x0000000000000F00), // OctadHi LaneBitmask(0x00000000000000FC), // OctadLo LaneBitmask(0x0000000000000001), // QuadAR0 LaneBitmask(0x0000000000000002), // QuadAR1 LaneBitmask(0x0000000000000004), // QuadAR2 LaneBitmask(0x0000000000000008), // QuadAR3 LaneBitmask(0x00000000000000CC), // QuadHi LaneBitmask(0x0000000000000030), // QuadLo LaneBitmask(0x0000000000000010), // SubRegHi LaneBitmask(0x0000000000000020), // SubRegLo LaneBitmask(0x0000000000000040), // QuadHi_then_SubRegHi LaneBitmask(0x0000000000000080), // QuadHi_then_SubRegLo LaneBitmask(0x0000000000000C00), // OctadHi_then_QuadHi LaneBitmask(0x0000000000000300), // OctadHi_then_QuadLo LaneBitmask(0x0000000000000100), // OctadHi_then_SubRegHi LaneBitmask(0x0000000000000200), // OctadHi_then_SubRegLo LaneBitmask(0x0000000000000400), // OctadHi_then_QuadHi_then_SubRegHi LaneBitmask(0x0000000000000800), // OctadHi_then_QuadHi_then_SubRegLo }; static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { // Mode = 0 (Default) { 32, 32, 32, /*VTLists+*/8 }, // AR { 32, 32, 32, /*VTLists+*/2 }, // MR { 32, 32, 32, /*VTLists+*/0 }, // ACC { 64, 64, 64, /*VTLists+*/12 }, // ARPair { 64, 64, 64, /*VTLists+*/12 }, // ARPair_with_SubRegHi { 64, 64, 64, /*VTLists+*/5 }, // MRPair { 64, 64, 64, /*VTLists+*/15 }, // ACCPair { 128, 128, 64, /*VTLists+*/17 }, // ARQuad { 128, 128, 64, /*VTLists+*/17 }, // ARQuad_with_QuadHi { 128, 128, 64, /*VTLists+*/17 }, // ACCQuad { 256, 256, 64, /*VTLists+*/19 }, // AROctad { 256, 256, 64, /*VTLists+*/19 }, // AROctad_with_OctadHi { 256, 256, 64, /*VTLists+*/19 }, // AROctad_with_OctadHi_then_QuadHi }; static const uint32_t ARSubClassMask[] = { 0x00000001, 0x00001910, // SubRegHi 0x00001910, // SubRegLo 0x00001900, // QuadHi_then_SubRegHi 0x00001900, // QuadHi_then_SubRegLo 0x00001000, // OctadHi_then_SubRegHi 0x00001000, // OctadHi_then_SubRegLo 0x00001000, // OctadHi_then_QuadHi_then_SubRegHi 0x00001000, // OctadHi_then_QuadHi_then_SubRegLo }; static const uint32_t MRSubClassMask[] = { 0x00000002, 0x00000020, // SubRegHi 0x00000020, // SubRegLo }; static const uint32_t ACCSubClassMask[] = { 0x00000004, 0x00000240, // SubRegHi 0x00000240, // SubRegLo 0x00000200, // QuadHi_then_SubRegHi 0x00000200, // QuadHi_then_SubRegLo }; static const uint32_t ARPairSubClassMask[] = { 0x00000018, 0x00001900, // QuadHi 0x00001900, // QuadLo 0x00001000, // OctadHi_then_QuadHi 0x00001000, // OctadHi_then_QuadLo }; static const uint32_t ARPair_with_SubRegHiSubClassMask[] = { 0x00000010, 0x00001900, // QuadHi 0x00001900, // QuadLo 0x00001000, // OctadHi_then_QuadHi 0x00001000, // OctadHi_then_QuadLo }; static const uint32_t MRPairSubClassMask[] = { 0x00000020, }; static const uint32_t ACCPairSubClassMask[] = { 0x00000040, 0x00000200, // QuadHi 0x00000200, // QuadLo }; static const uint32_t ARQuadSubClassMask[] = { 0x00000180, 0x00001800, // OctadHi 0x00001800, // OctadLo }; static const uint32_t ARQuad_with_QuadHiSubClassMask[] = { 0x00000100, 0x00001000, // OctadHi 0x00001800, // OctadLo }; static const uint32_t ACCQuadSubClassMask[] = { 0x00000200, }; static const uint32_t AROctadSubClassMask[] = { 0x00001c00, }; static const uint32_t AROctad_with_OctadHiSubClassMask[] = { 0x00001800, }; static const uint32_t AROctad_with_OctadHi_then_QuadHiSubClassMask[] = { 0x00001000, }; static const uint16_t SuperRegIdxSeqs[] = { /* 0 */ 1, 2, 0, /* 3 */ 7, 8, 0, /* 6 */ 9, 10, 0, /* 9 */ 9, 10, 11, 12, 0, /* 14 */ 7, 8, 13, 14, 0, /* 19 */ 9, 10, 11, 12, 15, 16, 17, 18, 0, }; static unsigned const ARPair_with_SubRegHiSuperclasses[] = { Colossus::ARPairRegClassID, }; static unsigned const ARQuad_with_QuadHiSuperclasses[] = { Colossus::ARQuadRegClassID, }; static unsigned const AROctad_with_OctadHiSuperclasses[] = { Colossus::AROctadRegClassID, }; static unsigned const AROctad_with_OctadHi_then_QuadHiSuperclasses[] = { Colossus::AROctadRegClassID, Colossus::AROctad_with_OctadHiRegClassID, }; namespace Colossus { // Register class instances extern const TargetRegisterClass ARRegClass = { &ColossusMCRegisterClasses[ARRegClassID], ARSubClassMask, SuperRegIdxSeqs + 19, LaneBitmask(0x0000000000000001), 0, false, 0x00, /* TSFlags */ false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass MRRegClass = { &ColossusMCRegisterClasses[MRRegClassID], MRSubClassMask, SuperRegIdxSeqs + 6, LaneBitmask(0x0000000000000001), 0, false, 0x00, /* TSFlags */ false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass ACCRegClass = { &ColossusMCRegisterClasses[ACCRegClassID], ACCSubClassMask, SuperRegIdxSeqs + 9, LaneBitmask(0x0000000000000001), 0, false, 0x00, /* TSFlags */ false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass ARPairRegClass = { &ColossusMCRegisterClasses[ARPairRegClassID], ARPairSubClassMask, SuperRegIdxSeqs + 14, LaneBitmask(0x0000000000000030), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass ARPair_with_SubRegHiRegClass = { &ColossusMCRegisterClasses[ARPair_with_SubRegHiRegClassID], ARPair_with_SubRegHiSubClassMask, SuperRegIdxSeqs + 14, LaneBitmask(0x0000000000000030), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ ARPair_with_SubRegHiSuperclasses, 1, nullptr }; extern const TargetRegisterClass MRPairRegClass = { &ColossusMCRegisterClasses[MRPairRegClassID], MRPairSubClassMask, SuperRegIdxSeqs + 2, LaneBitmask(0x0000000000000030), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass ACCPairRegClass = { &ColossusMCRegisterClasses[ACCPairRegClassID], ACCPairSubClassMask, SuperRegIdxSeqs + 3, LaneBitmask(0x0000000000000030), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass ARQuadRegClass = { &ColossusMCRegisterClasses[ARQuadRegClassID], ARQuadSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000000000000FC), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass ARQuad_with_QuadHiRegClass = { &ColossusMCRegisterClasses[ARQuad_with_QuadHiRegClassID], ARQuad_with_QuadHiSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000000000000FC), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ ARQuad_with_QuadHiSuperclasses, 1, nullptr }; extern const TargetRegisterClass ACCQuadRegClass = { &ColossusMCRegisterClasses[ACCQuadRegClassID], ACCQuadSubClassMask, SuperRegIdxSeqs + 2, LaneBitmask(0x00000000000000FC), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass AROctadRegClass = { &ColossusMCRegisterClasses[AROctadRegClassID], AROctadSubClassMask, SuperRegIdxSeqs + 2, LaneBitmask(0x0000000000000FFC), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ nullptr, 0, nullptr }; extern const TargetRegisterClass AROctad_with_OctadHiRegClass = { &ColossusMCRegisterClasses[AROctad_with_OctadHiRegClassID], AROctad_with_OctadHiSubClassMask, SuperRegIdxSeqs + 2, LaneBitmask(0x0000000000000FFC), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ AROctad_with_OctadHiSuperclasses, 1, nullptr }; extern const TargetRegisterClass AROctad_with_OctadHi_then_QuadHiRegClass = { &ColossusMCRegisterClasses[AROctad_with_OctadHi_then_QuadHiRegClassID], AROctad_with_OctadHi_then_QuadHiSubClassMask, SuperRegIdxSeqs + 2, LaneBitmask(0x0000000000000FFC), 0, false, 0x00, /* TSFlags */ true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ AROctad_with_OctadHi_then_QuadHiSuperclasses, 2, nullptr }; } // end namespace Colossus namespace { const TargetRegisterClass *const RegisterClasses[] = { &Colossus::ARRegClass, &Colossus::MRRegClass, &Colossus::ACCRegClass, &Colossus::ARPairRegClass, &Colossus::ARPair_with_SubRegHiRegClass, &Colossus::MRPairRegClass, &Colossus::ACCPairRegClass, &Colossus::ARQuadRegClass, &Colossus::ARQuad_with_QuadHiRegClass, &Colossus::ACCQuadRegClass, &Colossus::AROctadRegClass, &Colossus::AROctad_with_OctadHiRegClass, &Colossus::AROctad_with_OctadHi_then_QuadHiRegClass, }; } // end anonymous namespace static const uint8_t CostPerUseTable[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const bool InAllocatableClassTable[] = { false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, }; static const TargetRegisterInfoDesc ColossusRegInfoDesc = { // Extra Descriptors CostPerUseTable, 1, InAllocatableClassTable}; unsigned ColossusGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { static const uint8_t RowMap[18] = { 0, 1, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, }; static const uint8_t Rows[4][18] = { { 0, 0, 0, 0, 0, 0, Colossus::OctadHi_then_QuadHi, Colossus::OctadHi_then_QuadLo, Colossus::OctadHi_then_SubRegHi, Colossus::OctadHi_then_SubRegLo, Colossus::OctadHi_then_QuadHi_then_SubRegHi, Colossus::OctadHi_then_QuadHi_then_SubRegLo, 0, 0, 0, 0, 0, 0, }, { 0, 0, 0, 0, 0, 0, Colossus::QuadHi, Colossus::QuadLo, Colossus::SubRegHi, Colossus::SubRegLo, Colossus::QuadHi_then_SubRegHi, Colossus::QuadHi_then_SubRegLo, 0, 0, 0, 0, 0, 0, }, { 0, 0, Colossus::QuadAR2, Colossus::QuadAR3, 0, 0, 0, 0, Colossus::QuadHi_then_SubRegHi, Colossus::QuadHi_then_SubRegLo, 0, 0, 0, 0, 0, 0, 0, 0, }, { 0, 0, 0, 0, 0, 0, 0, 0, Colossus::OctadHi_then_QuadHi_then_SubRegHi, Colossus::OctadHi_then_QuadHi_then_SubRegLo, 0, 0, 0, 0, 0, 0, 0, 0, }, }; --IdxA; assert(IdxA < 18); (void) IdxA; --IdxB; assert(IdxB < 18); return Rows[RowMap[IdxA]][IdxB]; } struct MaskRolOp { LaneBitmask Mask; uint8_t RotateLeft; }; static const MaskRolOp LaneMaskComposeSequences[] = { { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 12 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 14 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 16 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 18 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 20 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 } // Sequence 22 }; static const uint8_t CompositeSequences[] = { 0, // to OctadHi 2, // to OctadLo 2, // to QuadAR0 4, // to QuadAR1 6, // to QuadAR2 8, // to QuadAR3 6, // to QuadHi 2, // to QuadLo 0, // to SubRegHi 10, // to SubRegLo 12, // to QuadHi_then_SubRegHi 14, // to QuadHi_then_SubRegLo 12, // to OctadHi_then_QuadHi 0, // to OctadHi_then_QuadLo 16, // to OctadHi_then_SubRegHi 18, // to OctadHi_then_SubRegLo 20, // to OctadHi_then_QuadHi_then_SubRegHi 22 // to OctadHi_then_QuadHi_then_SubRegLo }; LaneBitmask ColossusGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { --IdxA; assert(IdxA < 18 && "Subregister index out of bounds"); LaneBitmask Result; for (const MaskRolOp *Ops = &LaneMaskComposeSequences[CompositeSequences[IdxA]]; Ops->Mask.any(); ++Ops) { LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); if (unsigned S = Ops->RotateLeft) Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); else Result |= LaneBitmask(M); } return Result; } LaneBitmask ColossusGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { LaneMask &= getSubRegIndexLaneMask(IdxA); --IdxA; assert(IdxA < 18 && "Subregister index out of bounds"); LaneBitmask Result; for (const MaskRolOp *Ops = &LaneMaskComposeSequences[CompositeSequences[IdxA]]; Ops->Mask.any(); ++Ops) { LaneBitmask::Type M = LaneMask.getAsInteger(); if (unsigned S = Ops->RotateLeft) Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); else Result |= LaneBitmask(M); } return Result; } const TargetRegisterClass *ColossusGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { static const uint8_t Table[13][18] = { { // AR 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 0, // QuadHi 0, // QuadLo 0, // SubRegHi 0, // SubRegLo 0, // QuadHi_then_SubRegHi 0, // QuadHi_then_SubRegLo 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // MR 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 0, // QuadHi 0, // QuadLo 0, // SubRegHi 0, // SubRegLo 0, // QuadHi_then_SubRegHi 0, // QuadHi_then_SubRegLo 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // ACC 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 0, // QuadHi 0, // QuadLo 0, // SubRegHi 0, // SubRegLo 0, // QuadHi_then_SubRegHi 0, // QuadHi_then_SubRegLo 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // ARPair 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 0, // QuadHi 0, // QuadLo 5, // SubRegHi -> ARPair_with_SubRegHi 5, // SubRegLo -> ARPair_with_SubRegHi 0, // QuadHi_then_SubRegHi 0, // QuadHi_then_SubRegLo 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // ARPair_with_SubRegHi 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 0, // QuadHi 0, // QuadLo 5, // SubRegHi -> ARPair_with_SubRegHi 5, // SubRegLo -> ARPair_with_SubRegHi 0, // QuadHi_then_SubRegHi 0, // QuadHi_then_SubRegLo 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // MRPair 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 0, // QuadHi 0, // QuadLo 6, // SubRegHi -> MRPair 6, // SubRegLo -> MRPair 0, // QuadHi_then_SubRegHi 0, // QuadHi_then_SubRegLo 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // ACCPair 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 0, // QuadHi 0, // QuadLo 7, // SubRegHi -> ACCPair 7, // SubRegLo -> ACCPair 0, // QuadHi_then_SubRegHi 0, // QuadHi_then_SubRegLo 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // ARQuad 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 9, // QuadHi -> ARQuad_with_QuadHi 9, // QuadLo -> ARQuad_with_QuadHi 9, // SubRegHi -> ARQuad_with_QuadHi 9, // SubRegLo -> ARQuad_with_QuadHi 9, // QuadHi_then_SubRegHi -> ARQuad_with_QuadHi 9, // QuadHi_then_SubRegLo -> ARQuad_with_QuadHi 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // ARQuad_with_QuadHi 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 9, // QuadHi -> ARQuad_with_QuadHi 9, // QuadLo -> ARQuad_with_QuadHi 9, // SubRegHi -> ARQuad_with_QuadHi 9, // SubRegLo -> ARQuad_with_QuadHi 9, // QuadHi_then_SubRegHi -> ARQuad_with_QuadHi 9, // QuadHi_then_SubRegLo -> ARQuad_with_QuadHi 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // ACCQuad 0, // OctadHi 0, // OctadLo 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 10, // QuadHi -> ACCQuad 10, // QuadLo -> ACCQuad 10, // SubRegHi -> ACCQuad 10, // SubRegLo -> ACCQuad 10, // QuadHi_then_SubRegHi -> ACCQuad 10, // QuadHi_then_SubRegLo -> ACCQuad 0, // OctadHi_then_QuadHi 0, // OctadHi_then_QuadLo 0, // OctadHi_then_SubRegHi 0, // OctadHi_then_SubRegLo 0, // OctadHi_then_QuadHi_then_SubRegHi 0, // OctadHi_then_QuadHi_then_SubRegLo }, { // AROctad 12, // OctadHi -> AROctad_with_OctadHi 12, // OctadLo -> AROctad_with_OctadHi 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 12, // QuadHi -> AROctad_with_OctadHi 12, // QuadLo -> AROctad_with_OctadHi 12, // SubRegHi -> AROctad_with_OctadHi 12, // SubRegLo -> AROctad_with_OctadHi 12, // QuadHi_then_SubRegHi -> AROctad_with_OctadHi 12, // QuadHi_then_SubRegLo -> AROctad_with_OctadHi 13, // OctadHi_then_QuadHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadLo -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_SubRegLo -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadHi_then_SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadHi_then_SubRegLo -> AROctad_with_OctadHi_then_QuadHi }, { // AROctad_with_OctadHi 12, // OctadHi -> AROctad_with_OctadHi 12, // OctadLo -> AROctad_with_OctadHi 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 12, // QuadHi -> AROctad_with_OctadHi 12, // QuadLo -> AROctad_with_OctadHi 12, // SubRegHi -> AROctad_with_OctadHi 12, // SubRegLo -> AROctad_with_OctadHi 12, // QuadHi_then_SubRegHi -> AROctad_with_OctadHi 12, // QuadHi_then_SubRegLo -> AROctad_with_OctadHi 13, // OctadHi_then_QuadHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadLo -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_SubRegLo -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadHi_then_SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadHi_then_SubRegLo -> AROctad_with_OctadHi_then_QuadHi }, { // AROctad_with_OctadHi_then_QuadHi 13, // OctadHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadLo -> AROctad_with_OctadHi_then_QuadHi 0, // QuadAR0 0, // QuadAR1 0, // QuadAR2 0, // QuadAR3 13, // QuadHi -> AROctad_with_OctadHi_then_QuadHi 13, // QuadLo -> AROctad_with_OctadHi_then_QuadHi 13, // SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // SubRegLo -> AROctad_with_OctadHi_then_QuadHi 13, // QuadHi_then_SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // QuadHi_then_SubRegLo -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadLo -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_SubRegLo -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadHi_then_SubRegHi -> AROctad_with_OctadHi_then_QuadHi 13, // OctadHi_then_QuadHi_then_SubRegLo -> AROctad_with_OctadHi_then_QuadHi }, }; assert(RC && "Missing regclass"); if (!Idx) return RC; --Idx; assert(Idx < 18 && "Bad subreg"); unsigned TV = Table[RC->getID()][Idx]; return TV ? getRegClass(TV - 1) : nullptr; } const TargetRegisterClass *ColossusGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const { static const uint8_t Table[13][18] = { { // AR 0, // AR:OctadHi 0, // AR:OctadLo 0, // AR:QuadAR0 0, // AR:QuadAR1 0, // AR:QuadAR2 0, // AR:QuadAR3 0, // AR:QuadHi 0, // AR:QuadLo 0, // AR:SubRegHi 0, // AR:SubRegLo 0, // AR:QuadHi_then_SubRegHi 0, // AR:QuadHi_then_SubRegLo 0, // AR:OctadHi_then_QuadHi 0, // AR:OctadHi_then_QuadLo 0, // AR:OctadHi_then_SubRegHi 0, // AR:OctadHi_then_SubRegLo 0, // AR:OctadHi_then_QuadHi_then_SubRegHi 0, // AR:OctadHi_then_QuadHi_then_SubRegLo }, { // MR 0, // MR:OctadHi 0, // MR:OctadLo 0, // MR:QuadAR0 0, // MR:QuadAR1 0, // MR:QuadAR2 0, // MR:QuadAR3 0, // MR:QuadHi 0, // MR:QuadLo 0, // MR:SubRegHi 0, // MR:SubRegLo 0, // MR:QuadHi_then_SubRegHi 0, // MR:QuadHi_then_SubRegLo 0, // MR:OctadHi_then_QuadHi 0, // MR:OctadHi_then_QuadLo 0, // MR:OctadHi_then_SubRegHi 0, // MR:OctadHi_then_SubRegLo 0, // MR:OctadHi_then_QuadHi_then_SubRegHi 0, // MR:OctadHi_then_QuadHi_then_SubRegLo }, { // ACC 0, // ACC:OctadHi 0, // ACC:OctadLo 0, // ACC:QuadAR0 0, // ACC:QuadAR1 0, // ACC:QuadAR2 0, // ACC:QuadAR3 0, // ACC:QuadHi 0, // ACC:QuadLo 0, // ACC:SubRegHi 0, // ACC:SubRegLo 0, // ACC:QuadHi_then_SubRegHi 0, // ACC:QuadHi_then_SubRegLo 0, // ACC:OctadHi_then_QuadHi 0, // ACC:OctadHi_then_QuadLo 0, // ACC:OctadHi_then_SubRegHi 0, // ACC:OctadHi_then_SubRegLo 0, // ACC:OctadHi_then_QuadHi_then_SubRegHi 0, // ACC:OctadHi_then_QuadHi_then_SubRegLo }, { // ARPair 0, // ARPair:OctadHi 0, // ARPair:OctadLo 0, // ARPair:QuadAR0 0, // ARPair:QuadAR1 0, // ARPair:QuadAR2 0, // ARPair:QuadAR3 0, // ARPair:QuadHi 0, // ARPair:QuadLo 1, // ARPair:SubRegHi -> AR 1, // ARPair:SubRegLo -> AR 0, // ARPair:QuadHi_then_SubRegHi 0, // ARPair:QuadHi_then_SubRegLo 0, // ARPair:OctadHi_then_QuadHi 0, // ARPair:OctadHi_then_QuadLo 0, // ARPair:OctadHi_then_SubRegHi 0, // ARPair:OctadHi_then_SubRegLo 0, // ARPair:OctadHi_then_QuadHi_then_SubRegHi 0, // ARPair:OctadHi_then_QuadHi_then_SubRegLo }, { // ARPair_with_SubRegHi 0, // ARPair_with_SubRegHi:OctadHi 0, // ARPair_with_SubRegHi:OctadLo 0, // ARPair_with_SubRegHi:QuadAR0 0, // ARPair_with_SubRegHi:QuadAR1 0, // ARPair_with_SubRegHi:QuadAR2 0, // ARPair_with_SubRegHi:QuadAR3 0, // ARPair_with_SubRegHi:QuadHi 0, // ARPair_with_SubRegHi:QuadLo 1, // ARPair_with_SubRegHi:SubRegHi -> AR 1, // ARPair_with_SubRegHi:SubRegLo -> AR 0, // ARPair_with_SubRegHi:QuadHi_then_SubRegHi 0, // ARPair_with_SubRegHi:QuadHi_then_SubRegLo 0, // ARPair_with_SubRegHi:OctadHi_then_QuadHi 0, // ARPair_with_SubRegHi:OctadHi_then_QuadLo 0, // ARPair_with_SubRegHi:OctadHi_then_SubRegHi 0, // ARPair_with_SubRegHi:OctadHi_then_SubRegLo 0, // ARPair_with_SubRegHi:OctadHi_then_QuadHi_then_SubRegHi 0, // ARPair_with_SubRegHi:OctadHi_then_QuadHi_then_SubRegLo }, { // MRPair 0, // MRPair:OctadHi 0, // MRPair:OctadLo 0, // MRPair:QuadAR0 0, // MRPair:QuadAR1 0, // MRPair:QuadAR2 0, // MRPair:QuadAR3 0, // MRPair:QuadHi 0, // MRPair:QuadLo 2, // MRPair:SubRegHi -> MR 2, // MRPair:SubRegLo -> MR 0, // MRPair:QuadHi_then_SubRegHi 0, // MRPair:QuadHi_then_SubRegLo 0, // MRPair:OctadHi_then_QuadHi 0, // MRPair:OctadHi_then_QuadLo 0, // MRPair:OctadHi_then_SubRegHi 0, // MRPair:OctadHi_then_SubRegLo 0, // MRPair:OctadHi_then_QuadHi_then_SubRegHi 0, // MRPair:OctadHi_then_QuadHi_then_SubRegLo }, { // ACCPair 0, // ACCPair:OctadHi 0, // ACCPair:OctadLo 0, // ACCPair:QuadAR0 0, // ACCPair:QuadAR1 0, // ACCPair:QuadAR2 0, // ACCPair:QuadAR3 0, // ACCPair:QuadHi 0, // ACCPair:QuadLo 3, // ACCPair:SubRegHi -> ACC 3, // ACCPair:SubRegLo -> ACC 0, // ACCPair:QuadHi_then_SubRegHi 0, // ACCPair:QuadHi_then_SubRegLo 0, // ACCPair:OctadHi_then_QuadHi 0, // ACCPair:OctadHi_then_QuadLo 0, // ACCPair:OctadHi_then_SubRegHi 0, // ACCPair:OctadHi_then_SubRegLo 0, // ACCPair:OctadHi_then_QuadHi_then_SubRegHi 0, // ACCPair:OctadHi_then_QuadHi_then_SubRegLo }, { // ARQuad 0, // ARQuad:OctadHi 0, // ARQuad:OctadLo 0, // ARQuad:QuadAR0 0, // ARQuad:QuadAR1 0, // ARQuad:QuadAR2 0, // ARQuad:QuadAR3 5, // ARQuad:QuadHi -> ARPair_with_SubRegHi 5, // ARQuad:QuadLo -> ARPair_with_SubRegHi 1, // ARQuad:SubRegHi -> AR 1, // ARQuad:SubRegLo -> AR 1, // ARQuad:QuadHi_then_SubRegHi -> AR 1, // ARQuad:QuadHi_then_SubRegLo -> AR 0, // ARQuad:OctadHi_then_QuadHi 0, // ARQuad:OctadHi_then_QuadLo 0, // ARQuad:OctadHi_then_SubRegHi 0, // ARQuad:OctadHi_then_SubRegLo 0, // ARQuad:OctadHi_then_QuadHi_then_SubRegHi 0, // ARQuad:OctadHi_then_QuadHi_then_SubRegLo }, { // ARQuad_with_QuadHi 0, // ARQuad_with_QuadHi:OctadHi 0, // ARQuad_with_QuadHi:OctadLo 0, // ARQuad_with_QuadHi:QuadAR0 0, // ARQuad_with_QuadHi:QuadAR1 0, // ARQuad_with_QuadHi:QuadAR2 0, // ARQuad_with_QuadHi:QuadAR3 5, // ARQuad_with_QuadHi:QuadHi -> ARPair_with_SubRegHi 5, // ARQuad_with_QuadHi:QuadLo -> ARPair_with_SubRegHi 1, // ARQuad_with_QuadHi:SubRegHi -> AR 1, // ARQuad_with_QuadHi:SubRegLo -> AR 1, // ARQuad_with_QuadHi:QuadHi_then_SubRegHi -> AR 1, // ARQuad_with_QuadHi:QuadHi_then_SubRegLo -> AR 0, // ARQuad_with_QuadHi:OctadHi_then_QuadHi 0, // ARQuad_with_QuadHi:OctadHi_then_QuadLo 0, // ARQuad_with_QuadHi:OctadHi_then_SubRegHi 0, // ARQuad_with_QuadHi:OctadHi_then_SubRegLo 0, // ARQuad_with_QuadHi:OctadHi_then_QuadHi_then_SubRegHi 0, // ARQuad_with_QuadHi:OctadHi_then_QuadHi_then_SubRegLo }, { // ACCQuad 0, // ACCQuad:OctadHi 0, // ACCQuad:OctadLo 0, // ACCQuad:QuadAR0 0, // ACCQuad:QuadAR1 0, // ACCQuad:QuadAR2 0, // ACCQuad:QuadAR3 7, // ACCQuad:QuadHi -> ACCPair 7, // ACCQuad:QuadLo -> ACCPair 3, // ACCQuad:SubRegHi -> ACC 3, // ACCQuad:SubRegLo -> ACC 3, // ACCQuad:QuadHi_then_SubRegHi -> ACC 3, // ACCQuad:QuadHi_then_SubRegLo -> ACC 0, // ACCQuad:OctadHi_then_QuadHi 0, // ACCQuad:OctadHi_then_QuadLo 0, // ACCQuad:OctadHi_then_SubRegHi 0, // ACCQuad:OctadHi_then_SubRegLo 0, // ACCQuad:OctadHi_then_QuadHi_then_SubRegHi 0, // ACCQuad:OctadHi_then_QuadHi_then_SubRegLo }, { // AROctad 8, // AROctad:OctadHi -> ARQuad 9, // AROctad:OctadLo -> ARQuad_with_QuadHi 0, // AROctad:QuadAR0 0, // AROctad:QuadAR1 0, // AROctad:QuadAR2 0, // AROctad:QuadAR3 5, // AROctad:QuadHi -> ARPair_with_SubRegHi 5, // AROctad:QuadLo -> ARPair_with_SubRegHi 1, // AROctad:SubRegHi -> AR 1, // AROctad:SubRegLo -> AR 1, // AROctad:QuadHi_then_SubRegHi -> AR 1, // AROctad:QuadHi_then_SubRegLo -> AR 5, // AROctad:OctadHi_then_QuadHi -> ARPair_with_SubRegHi 5, // AROctad:OctadHi_then_QuadLo -> ARPair_with_SubRegHi 1, // AROctad:OctadHi_then_SubRegHi -> AR 1, // AROctad:OctadHi_then_SubRegLo -> AR 1, // AROctad:OctadHi_then_QuadHi_then_SubRegHi -> AR 1, // AROctad:OctadHi_then_QuadHi_then_SubRegLo -> AR }, { // AROctad_with_OctadHi 8, // AROctad_with_OctadHi:OctadHi -> ARQuad 9, // AROctad_with_OctadHi:OctadLo -> ARQuad_with_QuadHi 0, // AROctad_with_OctadHi:QuadAR0 0, // AROctad_with_OctadHi:QuadAR1 0, // AROctad_with_OctadHi:QuadAR2 0, // AROctad_with_OctadHi:QuadAR3 5, // AROctad_with_OctadHi:QuadHi -> ARPair_with_SubRegHi 5, // AROctad_with_OctadHi:QuadLo -> ARPair_with_SubRegHi 1, // AROctad_with_OctadHi:SubRegHi -> AR 1, // AROctad_with_OctadHi:SubRegLo -> AR 1, // AROctad_with_OctadHi:QuadHi_then_SubRegHi -> AR 1, // AROctad_with_OctadHi:QuadHi_then_SubRegLo -> AR 5, // AROctad_with_OctadHi:OctadHi_then_QuadHi -> ARPair_with_SubRegHi 5, // AROctad_with_OctadHi:OctadHi_then_QuadLo -> ARPair_with_SubRegHi 1, // AROctad_with_OctadHi:OctadHi_then_SubRegHi -> AR 1, // AROctad_with_OctadHi:OctadHi_then_SubRegLo -> AR 1, // AROctad_with_OctadHi:OctadHi_then_QuadHi_then_SubRegHi -> AR 1, // AROctad_with_OctadHi:OctadHi_then_QuadHi_then_SubRegLo -> AR }, { // AROctad_with_OctadHi_then_QuadHi 9, // AROctad_with_OctadHi_then_QuadHi:OctadHi -> ARQuad_with_QuadHi 9, // AROctad_with_OctadHi_then_QuadHi:OctadLo -> ARQuad_with_QuadHi 0, // AROctad_with_OctadHi_then_QuadHi:QuadAR0 0, // AROctad_with_OctadHi_then_QuadHi:QuadAR1 0, // AROctad_with_OctadHi_then_QuadHi:QuadAR2 0, // AROctad_with_OctadHi_then_QuadHi:QuadAR3 5, // AROctad_with_OctadHi_then_QuadHi:QuadHi -> ARPair_with_SubRegHi 5, // AROctad_with_OctadHi_then_QuadHi:QuadLo -> ARPair_with_SubRegHi 1, // AROctad_with_OctadHi_then_QuadHi:SubRegHi -> AR 1, // AROctad_with_OctadHi_then_QuadHi:SubRegLo -> AR 1, // AROctad_with_OctadHi_then_QuadHi:QuadHi_then_SubRegHi -> AR 1, // AROctad_with_OctadHi_then_QuadHi:QuadHi_then_SubRegLo -> AR 5, // AROctad_with_OctadHi_then_QuadHi:OctadHi_then_QuadHi -> ARPair_with_SubRegHi 5, // AROctad_with_OctadHi_then_QuadHi:OctadHi_then_QuadLo -> ARPair_with_SubRegHi 1, // AROctad_with_OctadHi_then_QuadHi:OctadHi_then_SubRegHi -> AR 1, // AROctad_with_OctadHi_then_QuadHi:OctadHi_then_SubRegLo -> AR 1, // AROctad_with_OctadHi_then_QuadHi:OctadHi_then_QuadHi_then_SubRegHi -> AR 1, // AROctad_with_OctadHi_then_QuadHi:OctadHi_then_QuadHi_then_SubRegLo -> AR }, }; assert(RC && "Missing regclass"); if (!Idx) return RC; --Idx; assert(Idx < 18 && "Bad subreg"); unsigned TV = Table[RC->getID()][Idx]; return TV ? getRegClass(TV - 1) : nullptr; } /// Get the weight in units of pressure for this register class. const RegClassWeight &ColossusGenRegisterInfo:: getRegClassWeight(const TargetRegisterClass *RC) const { static const RegClassWeight RCWeightTable[] = { {1, 16}, // AR {1, 16}, // MR {1, 8}, // ACC {2, 32}, // ARPair {2, 16}, // ARPair_with_SubRegHi {2, 16}, // MRPair {2, 8}, // ACCPair {4, 64}, // ARQuad {4, 16}, // ARQuad_with_QuadHi {4, 8}, // ACCQuad {8, 128}, // AROctad {8, 16}, // AROctad_with_OctadHi {8, 8}, // AROctad_with_OctadHi_then_QuadHi }; return RCWeightTable[RC->getID()]; } /// Get the weight in units of pressure for this register unit. unsigned ColossusGenRegisterInfo:: getRegUnitWeight(unsigned RegUnit) const { assert(RegUnit < 74 && "invalid register unit"); static const uint8_t RUWeightTable[] = { 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; return RUWeightTable[RegUnit]; } // Get the number of dimensions of register pressure. unsigned ColossusGenRegisterInfo::getNumRegPressureSets() const { return 13; } // Get the name of this register unit pressure set. const char *ColossusGenRegisterInfo:: getRegPressureSetName(unsigned Idx) const { static const char *PressureNameTable[] = { "ACC", "AROctad_with_OctadHi_then_QuadHi", "AROctad_with_OctadHi", "MR", "AR", "ARPair", "ARPair_with_AROctad_with_OctadHi", "AROctad", "ARQuad", "AR_with_AROctad", "ARPair_with_ARQuad", "ARPair_with_AROctad", "ARQuad_with_AROctad", }; return PressureNameTable[Idx]; } // Get the register unit pressure limit for this dimension. // This limit must be adjusted dynamically for reserved registers. unsigned ColossusGenRegisterInfo:: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { static const uint8_t PressureLimitTable[] = { 8, // 0: ACC 8, // 1: AROctad_with_OctadHi_then_QuadHi 16, // 2: AROctad_with_OctadHi 16, // 3: MR 20, // 4: AR 32, // 5: ARPair 36, // 6: ARPair_with_AROctad_with_OctadHi 128, // 7: AROctad 64, // 8: ARQuad 132, // 9: AR_with_AROctad 80, // 10: ARPair_with_ARQuad 148, // 11: ARPair_with_AROctad 176, // 12: ARQuad_with_AROctad }; return PressureLimitTable[Idx]; } /// Table of pressure sets per register class or unit. static const int RCSetsTable[] = { /* 0 */ 0, -1, /* 2 */ 3, -1, /* 4 */ 5, 6, 10, 11, -1, /* 9 */ 8, 10, 12, -1, /* 13 */ 7, 9, 11, 12, -1, /* 18 */ 4, 5, 6, 8, 9, 10, 11, 12, -1, /* 27 */ 2, 4, 6, 7, 8, 9, 10, 11, 12, -1, /* 37 */ 1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, -1, }; /// Get the dimensions of register pressure impacted by this register class. /// Returns a -1 terminated array of pressure set IDs const int *ColossusGenRegisterInfo:: getRegClassPressureSets(const TargetRegisterClass *RC) const { static const uint8_t RCSetStartTable[] = { 18,2,0,4,18,2,0,9,18,0,13,27,37,}; return &RCSetsTable[RCSetStartTable[RC->getID()]]; } /// Get the dimensions of register pressure impacted by this register unit. /// Returns a -1 terminated array of pressure set IDs const int *ColossusGenRegisterInfo:: getRegUnitPressureSets(unsigned RegUnit) const { assert(RegUnit < 74 && "invalid register unit"); static const uint8_t RUSetStartTable[] = { 38,38,38,38,27,18,18,18,18,2,2,2,2,2,2,2,37,37,37,37,37,37,37,37,0,0,0,0,0,0,0,0,4,4,4,4,4,4,4,4,13,13,13,13,13,13,13,13,13,13,13,13,13,13,9,9,9,9,9,9,9,9,9,9,9,2,2,2,2,2,2,2,2,2,}; return &RCSetsTable[RUSetStartTable[RegUnit]]; } extern const MCRegisterDesc ColossusRegDesc[]; extern const int16_t ColossusRegDiffLists[]; extern const LaneBitmask ColossusLaneMaskLists[]; extern const char ColossusRegStrings[]; extern const char ColossusRegClassStrings[]; extern const MCPhysReg ColossusRegUnitRoots[][2]; extern const uint16_t ColossusSubRegIdxLists[]; extern const uint16_t ColossusRegEncodingTable[]; // Colossus Dwarf<->LLVM register mappings. extern const MCRegisterInfo::DwarfLLVMRegPair ColossusDwarfFlavour0Dwarf2L[]; extern const unsigned ColossusDwarfFlavour0Dwarf2LSize; extern const MCRegisterInfo::DwarfLLVMRegPair ColossusEHFlavour0Dwarf2L[]; extern const unsigned ColossusEHFlavour0Dwarf2LSize; extern const MCRegisterInfo::DwarfLLVMRegPair ColossusDwarfFlavour0L2Dwarf[]; extern const unsigned ColossusDwarfFlavour0L2DwarfSize; extern const MCRegisterInfo::DwarfLLVMRegPair ColossusEHFlavour0L2Dwarf[]; extern const unsigned ColossusEHFlavour0L2DwarfSize; ColossusGenRegisterInfo:: ColossusGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC, unsigned HwMode) : TargetRegisterInfo(&ColossusRegInfoDesc, RegisterClasses, RegisterClasses+13, SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable, LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) { InitMCRegisterInfo(ColossusRegDesc, 103, RA, PC, ColossusMCRegisterClasses, 13, ColossusRegUnitRoots, 74, ColossusRegDiffLists, ColossusLaneMaskLists, ColossusRegStrings, ColossusRegClassStrings, ColossusSubRegIdxLists, 19, ColossusRegEncodingTable); switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapDwarfRegsToLLVMRegs(ColossusDwarfFlavour0Dwarf2L, ColossusDwarfFlavour0Dwarf2LSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapDwarfRegsToLLVMRegs(ColossusEHFlavour0Dwarf2L, ColossusEHFlavour0Dwarf2LSize, true); break; } switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapLLVMRegsToDwarfRegs(ColossusDwarfFlavour0L2Dwarf, ColossusDwarfFlavour0L2DwarfSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapLLVMRegsToDwarfRegs(ColossusEHFlavour0L2Dwarf, ColossusEHFlavour0L2DwarfSize, true); break; } } static const MCPhysReg CC_Save_SaveList[] = { Colossus::M7, Colossus::BP, Colossus::FP, Colossus::LR, Colossus::A6, Colossus::A7, 0 }; static const uint32_t CC_Save_RegMask[] = { 0x070c04fc, 0x00009000, 0x20000000, 0x00000008, }; static const MCPhysReg CC_Save_BP_SaveList[] = { Colossus::M7, Colossus::FP, Colossus::LR, Colossus::A6, Colossus::A7, 0 }; static const uint32_t CC_Save_BP_RegMask[] = { 0x070c04dc, 0x00009000, 0x20000000, 0x00000000, }; static const MCPhysReg CC_Save_BP_AND_FP_SaveList[] = { Colossus::M7, Colossus::LR, Colossus::A6, Colossus::A7, 0 }; static const uint32_t CC_Save_BP_AND_FP_RegMask[] = { 0x070c049c, 0x00009000, 0x20000000, 0x00000000, }; static const MCPhysReg CC_Save_FP_SaveList[] = { Colossus::M7, Colossus::BP, Colossus::LR, Colossus::A6, Colossus::A7, 0 }; static const uint32_t CC_Save_FP_RegMask[] = { 0x070c04bc, 0x00009000, 0x20000000, 0x00000000, }; static const MCPhysReg CC_Save_Vertex_SaveList[] = { 0 }; static const uint32_t CC_Save_Vertex_RegMask[] = { 0x0700041c, 0x00008000, 0x00000000, 0x00000000, }; ArrayRef ColossusGenRegisterInfo::getRegMasks() const { static const uint32_t *const Masks[] = { CC_Save_RegMask, CC_Save_BP_RegMask, CC_Save_BP_AND_FP_RegMask, CC_Save_FP_RegMask, CC_Save_Vertex_RegMask, }; return ArrayRef(Masks); } bool ColossusGenRegisterInfo:: isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const { return false; } bool ColossusGenRegisterInfo:: isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const { return false; } bool ColossusGenRegisterInfo:: isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const { return false; } bool ColossusGenRegisterInfo:: isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const { return false; } bool ColossusGenRegisterInfo:: isConstantPhysReg(MCRegister PhysReg) const { return PhysReg == Colossus::AQZERO || PhysReg == Colossus::AZERO || PhysReg == Colossus::AZEROS || PhysReg == Colossus::MZERO || false; } ArrayRef ColossusGenRegisterInfo::getRegMaskNames() const { static const char *Names[] = { "CC_Save", "CC_Save_BP", "CC_Save_BP_AND_FP", "CC_Save_FP", "CC_Save_Vertex", }; return ArrayRef(Names); } const ColossusFrameLowering * ColossusGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { return static_cast( MF.getSubtarget().getFrameLowering()); } } // end namespace llvm #endif // GET_REGINFO_TARGET_DESC