/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Subtarget Enumeration Source Fragment                                      *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM

namespace llvm {
namespace Colossus {
enum {
  ModeArchIpu1 = 0,
  ModeArchIpu2 = 1,
  ModeArchIpu21 = 2,
  ModeBoth = 3,
  ModeSupervisor = 4,
  ModeWorker = 5,
  NumSubtargetFeatures = 6
};
} // end namespace Colossus
} // end namespace llvm

#endif // GET_SUBTARGETINFO_ENUM


#ifdef GET_SUBTARGETINFO_MACRO
#undef GET_SUBTARGETINFO_MACRO
#endif // GET_SUBTARGETINFO_MACRO


#ifdef GET_SUBTARGETINFO_MC_DESC
#undef GET_SUBTARGETINFO_MC_DESC

namespace llvm {
// Sorted (by key) array of values for CPU features.
extern const llvm::SubtargetFeatureKV ColossusFeatureKV[] = {
  { "both", "Both mode", Colossus::ModeBoth, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
  { "ipu1", "IPU target architecture", Colossus::ModeArchIpu1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
  { "ipu2", "IPU target architecture", Colossus::ModeArchIpu2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
  { "ipu21", "IPU target architecture", Colossus::ModeArchIpu21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
  { "supervisor", "Supervisor mode", Colossus::ModeSupervisor, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
  { "worker", "Worker mode", Colossus::ModeWorker, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
};

#ifdef DBGFIELD
#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
#endif
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define DBGFIELD(x) x,
#else
#define DBGFIELD(x)
#endif

// ===============================================================
// Data tables for the new per-operand machine model.

// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
extern const llvm::MCWriteProcResEntry ColossusWriteProcResTable[] = {
  { 0,  0,  0 }, // Invalid
  { 2,  1,   0}, // #1
  { 1,  1,   0}, // #2
  { 2,  0,   0} // #3
}; // ColossusWriteProcResTable

// {Cycles, WriteResourceID}
extern const llvm::MCWriteLatencyEntry ColossusWriteLatencyTable[] = {
  { 0,  0}, // Invalid
  { 1,  0}, // #1 WriteMain_WriteAux
  { 1,  0}, // #2 WriteMain_WriteFreeMain
  { 1,  0} // #3 WriteFreeMain
}; // ColossusWriteLatencyTable

// {UseIdx, WriteResourceID, Cycles}
extern const llvm::MCReadAdvanceEntry ColossusReadAdvanceTable[] = {
  {0,  0,  0}, // Invalid
}; // ColossusReadAdvanceTable

// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
static const llvm::MCSchedClassDesc ColossusCoissuedModelSchedClasses[] = {
  {DBGFIELD("InvalidSchedClass")  8191, false, false, false, 0, 0,  0, 0,  0, 0},
  {DBGFIELD("WriteMain")          1, false, false, false,  1, 1,  1, 1,  0, 0}, // #1
  {DBGFIELD("WriteAux")           1, false, false, false,  2, 1,  1, 1,  0, 0}, // #2
  {DBGFIELD("WriteMain_WriteFreeMain") 1, false, false, false,  1, 1,  2, 2,  0, 0}, // #3
  {DBGFIELD("WriteMain_WriteFreeMain_WriteFreeMain") 1, false, false, false,  1, 1,  1, 3,  0, 0}, // #4
  {DBGFIELD("COPY")               0, false, false, false,  3, 1,  0, 1,  0, 0}, // #5
}; // ColossusCoissuedModelSchedClasses

// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
static const llvm::MCSchedClassDesc ColossusSingleIssuedModelSchedClasses[] = {
  {DBGFIELD("InvalidSchedClass")  8191, false, false, false, 0, 0,  0, 0,  0, 0},
  {DBGFIELD("WriteMain")          1, false, false, false,  1, 1,  1, 1,  0, 0}, // #1
  {DBGFIELD("WriteAux")           1, false, false, false,  2, 1,  1, 1,  0, 0}, // #2
  {DBGFIELD("WriteMain_WriteFreeMain") 1, false, false, false,  1, 1,  1, 2,  0, 0}, // #3
  {DBGFIELD("WriteMain_WriteFreeMain_WriteFreeMain") 1, false, false, false,  1, 1,  1, 3,  0, 0}, // #4
  {DBGFIELD("COPY")               0, false, false, false,  3, 1,  0, 1,  0, 0}, // #5
}; // ColossusSingleIssuedModelSchedClasses

#undef DBGFIELD

static const llvm::MCSchedModel NoSchedModel = {
  MCSchedModel::DefaultIssueWidth,
  MCSchedModel::DefaultMicroOpBufferSize,
  MCSchedModel::DefaultLoopMicroOpBufferSize,
  MCSchedModel::DefaultLoadLatency,
  MCSchedModel::DefaultHighLatency,
  MCSchedModel::DefaultMispredictPenalty,
  false, // PostRAScheduler
  false, // CompleteModel
  false, // EnableIntervals
  0, // Processor ID
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
  nullptr, // No Itinerary
  nullptr // No extra processor descriptor
};

static const unsigned ColossusCoissuedModelProcResourceSubUnits[] = {
  0,  // Invalid
};

// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
static const llvm::MCProcResourceDesc ColossusCoissuedModelProcResources[] = {
  {"InvalidUnit", 0, 0, 0, 0},
  {"ColossusUnitAux", 1, 0, 0, nullptr}, // #1
  {"ColossusUnitMain", 1, 0, 0, nullptr}, // #2
};

static const llvm::MCSchedModel ColossusCoissuedModel = {
  2, // IssueWidth
  1, // MicroOpBufferSize
  MCSchedModel::DefaultLoopMicroOpBufferSize,
  1, // LoadLatency
  MCSchedModel::DefaultHighLatency,
  0, // MispredictPenalty
  false, // PostRAScheduler
  true, // CompleteModel
  false, // EnableIntervals
  1, // Processor ID
  ColossusCoissuedModelProcResources,
  ColossusCoissuedModelSchedClasses,
  3,
  6,
  nullptr, // No Itinerary
  nullptr // No extra processor descriptor
};

static const unsigned ColossusSingleIssuedModelProcResourceSubUnits[] = {
  0,  // Invalid
};

// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
static const llvm::MCProcResourceDesc ColossusSingleIssuedModelProcResources[] = {
  {"InvalidUnit", 0, 0, 0, 0},
  {"ColossusUnitAux", 1, 0, 0, nullptr}, // #1
  {"ColossusUnitMain", 1, 0, 0, nullptr}, // #2
};

static const llvm::MCSchedModel ColossusSingleIssuedModel = {
  1, // IssueWidth
  1, // MicroOpBufferSize
  MCSchedModel::DefaultLoopMicroOpBufferSize,
  1, // LoadLatency
  MCSchedModel::DefaultHighLatency,
  0, // MispredictPenalty
  false, // PostRAScheduler
  true, // CompleteModel
  false, // EnableIntervals
  2, // Processor ID
  ColossusSingleIssuedModelProcResources,
  ColossusSingleIssuedModelSchedClasses,
  3,
  6,
  nullptr, // No Itinerary
  nullptr // No extra processor descriptor
};

// Sorted (by key) array of values for CPU subtype.
extern const llvm::SubtargetSubTypeKV ColossusSubTypeKV[] = {
 { "ipu-generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &ColossusCoissuedModel },
 { "ipu-generic-single-issue", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &ColossusSingleIssuedModel },
 { "ipu1", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &ColossusCoissuedModel },
 { "ipu2", { { { 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &ColossusCoissuedModel },
 { "ipu21", { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &ColossusCoissuedModel },
};

// Sorted array of names of CPU subtypes, including aliases.
extern const llvm::StringRef ColossusNames[] = {
"ipu-generic",
"ipu-generic-single-issue",
"ipu1",
"ipu2",
"ipu21"};

namespace Colossus_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
    const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
  // Don't know how to resolve this scheduling class.
  return 0;
}
} // end namespace Colossus_MC

struct ColossusGenMCSubtargetInfo : public MCSubtargetInfo {
  ColossusGenMCSubtargetInfo(const Triple &TT,
    StringRef CPU, StringRef TuneCPU, StringRef FS,
    ArrayRef<StringRef> PN,
    ArrayRef<SubtargetFeatureKV> PF,
    ArrayRef<SubtargetSubTypeKV> PD,
    const MCWriteProcResEntry *WPR,
    const MCWriteLatencyEntry *WL,
    const MCReadAdvanceEntry *RA, const InstrStage *IS,
    const unsigned *OC, const unsigned *FP) :
      MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
                      WPR, WL, RA, IS, OC, FP) { }

  unsigned resolveVariantSchedClass(unsigned SchedClass,
      const MCInst *MI, const MCInstrInfo *MCII,
      unsigned CPUID) const override {
    return Colossus_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
  }
};

static inline MCSubtargetInfo *createColossusMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
  return new ColossusGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ColossusNames, ColossusFeatureKV, ColossusSubTypeKV, 
                      ColossusWriteProcResTable, ColossusWriteLatencyTable, ColossusReadAdvanceTable, 
                      nullptr, nullptr, nullptr);
}

} // end namespace llvm

#endif // GET_SUBTARGETINFO_MC_DESC


#ifdef GET_SUBTARGETINFO_TARGET_DESC
#undef GET_SUBTARGETINFO_TARGET_DESC

#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options.
void llvm::ColossusSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
  LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
  InitMCProcessorInfo(CPU, TuneCPU, FS);
  const FeatureBitset &Bits = getFeatureBits();
  if (Bits[Colossus::ModeArchIpu1] && ColossusArchVersion < Ipu1) ColossusArchVersion = Ipu1;
  if (Bits[Colossus::ModeArchIpu2] && ColossusArchVersion < Ipu2) ColossusArchVersion = Ipu2;
  if (Bits[Colossus::ModeArchIpu21] && ColossusArchVersion < Ipu21) ColossusArchVersion = Ipu21;
  if (Bits[Colossus::ModeBoth] && ExecutionMode < Both) ExecutionMode = Both;
  if (Bits[Colossus::ModeSupervisor] && ExecutionMode < Supervisor) ExecutionMode = Supervisor;
  if (Bits[Colossus::ModeWorker] && ExecutionMode < Worker) ExecutionMode = Worker;
}
#endif // GET_SUBTARGETINFO_TARGET_DESC


#ifdef GET_SUBTARGETINFO_HEADER
#undef GET_SUBTARGETINFO_HEADER

namespace llvm {
class DFAPacketizer;
namespace Colossus_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
} // end namespace Colossus_MC

struct ColossusGenSubtargetInfo : public TargetSubtargetInfo {
  explicit ColossusGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
public:
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
};
} // end namespace llvm

#endif // GET_SUBTARGETINFO_HEADER


#ifdef GET_SUBTARGETINFO_CTOR
#undef GET_SUBTARGETINFO_CTOR

#include "llvm/CodeGen/TargetSchedule.h"

namespace llvm {
extern const llvm::StringRef ColossusNames[];
extern const llvm::SubtargetFeatureKV ColossusFeatureKV[];
extern const llvm::SubtargetSubTypeKV ColossusSubTypeKV[];
extern const llvm::MCWriteProcResEntry ColossusWriteProcResTable[];
extern const llvm::MCWriteLatencyEntry ColossusWriteLatencyTable[];
extern const llvm::MCReadAdvanceEntry ColossusReadAdvanceTable[];
ColossusGenSubtargetInfo::ColossusGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
  : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(ColossusNames, 5), ArrayRef(ColossusFeatureKV, 6), ArrayRef(ColossusSubTypeKV, 5), 
                        ColossusWriteProcResTable, ColossusWriteLatencyTable, ColossusReadAdvanceTable, 
                        nullptr, nullptr, nullptr) {}

unsigned ColossusGenSubtargetInfo
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
  report_fatal_error("Expected a variant SchedClass");
} // ColossusGenSubtargetInfo::resolveSchedClass

unsigned ColossusGenSubtargetInfo
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
  return Colossus_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
} // ColossusGenSubtargetInfo::resolveVariantSchedClass

} // end namespace llvm

#endif // GET_SUBTARGETINFO_CTOR


#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS

#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS


#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS

#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS