//===-- ColossusInstrInfo.h - Colossus Instruction Information --*- C++ -*-===//
//    Copyright (c) 2023 Graphcore Ltd. All Rights Reserved.
//     Licensed under the Apache License, Version 2.0 (the "License");
//     you may not use this file except in compliance with the License.
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//
//        http://www.apache.org/licenses/LICENSE-2.0
//
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//     distributed under the License is distributed on an "AS IS" BASIS,
//     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//     See the License for the specific language governing permissions and
//     limitations under the License.
// --- LLVM Exceptions to the Apache 2.0 License ----
//
// As an exception, if, as a result of your compiling your source code, portions
// of this Software are embedded into an Object form of such source code, you
// may redistribute such embedded portions in such Object form without complying
// with the conditions of Sections 4(a), 4(b) and 4(d) of the License.
//
// In addition, if you combine or link compiled forms of this Software with
// software that is licensed under the GPLv2 ("Combined Software") and if a
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// 3), the indemnity provision (Section 9) or other Section of the License
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//
//===----------------------------------------------------------------------===//
//
// This file contains the Colossus implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_COLOSSUS_COLOSSUSINSTRINFO_H
#define LLVM_LIB_TARGET_COLOSSUS_COLOSSUSINSTRINFO_H

#include "ColossusRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"

#define GET_INSTRINFO_HEADER
#include "ColossusGenInstrInfo.inc"

namespace llvm {

class ColossusInstrInfo : public ColossusGenInstrInfo {
  const ColossusRegisterInfo RI;
  virtual void anchor();

public:
  ColossusInstrInfo();

  /// TargetInstrInfo is a superset of MRegister info.  As such, whenever a
  /// client has an instance of instruction info, it should always be able to
  /// get register info as well (through this method).
  const TargetRegisterInfo &getRegisterInfo() const { return RI; }

  virtual void
  copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
              const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
              bool KillSrc) const override;

  virtual void
  storeRegToStackSlot(MachineBasicBlock &MBB,
                      MachineBasicBlock::iterator MI,
                      Register SrcReg, bool isKill, int FrameIndex,
                      const TargetRegisterClass *RC,
                      const TargetRegisterInfo *TRI) const override;

  virtual void
  loadRegFromStackSlot(MachineBasicBlock &MBB,
                       MachineBasicBlock::iterator MI,
                       Register DestReg, int FrameIndex,
                       const TargetRegisterClass *RC,
                       const TargetRegisterInfo *TRI) const override;

  void expandF32ToI32(MachineBasicBlock &MBB,
                      MachineBasicBlock::iterator MI,
                      unsigned Opcode) const;

  void expandI32ToF32(MachineBasicBlock &MBB,
                      MachineBasicBlock::iterator MI,
                      unsigned Opcode) const;

  void expandF32OComparison(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
                            unsigned Opcode) const;

  void expandF32UComparison(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
                            unsigned Opcode) const;

  /// This function is called for all pseudo instructions that remain after
  /// register allocation.
  virtual bool
  expandPostRAPseudo(MachineInstr &MI) const override;

  virtual bool
  analyzeBranch(MachineBasicBlock &MBB,
                MachineBasicBlock *&TBB,
                MachineBasicBlock *&FBB,
                SmallVectorImpl<MachineOperand> &Cond,
                bool AllowModify) const override;

  virtual unsigned
  removeBranch(MachineBasicBlock &MBB,
               int *BytesRemoved = nullptr) const override;

  virtual unsigned
  insertBranch(MachineBasicBlock &MBB,
               MachineBasicBlock *TBB,
               MachineBasicBlock *FBB,
               ArrayRef<MachineOperand> Cond,
               const DebugLoc &DL,
               int *BytesAdded = nullptr) const override;

  virtual bool
  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;

  virtual bool isSchedulingBoundary(const MachineInstr &MI,
                                    const MachineBasicBlock *MBB,
                                    const MachineFunction &MF) const override;

  virtual bool canBeCSECandidate(const MachineInstr &MI) const override;

  /// Materialise constant values in a register/registers.
  void
  loadConstant32(MachineBasicBlock &MBB,
                 MachineBasicBlock::iterator MI,
                 unsigned Reg,
                 uint32_t Value,
                 bool IsRegDead = false) const;

  /// Create a machine-memory operand for a specific frame index.
  MachineMemOperand* getFrameIndexMMO(MachineBasicBlock &MBB,
                                      int FrameIndex,
                                      MachineMemOperand::Flags flags) const;

  /// Analyze loop L, which must be a single-basic-block loop, and if the
  /// conditions can be understood enough produce a PipelinerLoopInfo object.
  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
};

}

#endif