; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=colossus -mattr=+ipu1 | FileCheck %s
; RUN: llc < %s -march=colossus -mattr=+ipu2 | FileCheck %s

;===-----------------------------------------------------------------------===;
; icmp eq
;===-----------------------------------------------------------------------===;
define i1 @cmpeq_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpeq_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, %b
  ret i1 %1
}

define i1 @cmpeq_zero(i32 %a) {
; CHECK-LABEL: cmpeq_zero:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, 0
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, 0
  ret i1 %1
}

define i1 @cmpeq_zimm(i32 %a) {
; CHECK-LABEL: cmpeq_zimm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, 42
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, 42
  ret i1 %1
}

define i1 @cmpeq_large_zimm(i32 %a) {
; CHECK-LABEL: cmpeq_large_zimm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    setzi $m1, 977851
; CHECK-NEXT:    or $m1, $m1, 1380974592
; CHECK-NEXT:    cmpeq $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, 1381952443
  ret i1 %1
}

define i1 @cmpeq_large_immz(i32 %a) {
; CHECK-LABEL: cmpeq_large_immz:
; CHECK:       # %bb.0:
; CHECK-NEXT:    or $m1, $m15, 267386880
; CHECK-NEXT:    cmpeq $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, 267386880 ; bottom 20 bits are clear so no setzi required
  ret i1 %1
}

define i1 @cmpeq_simm(i32 %a) {
; CHECK-LABEL: cmpeq_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, -1
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, -1
  ret i1 %1
}

define i1 @cmpeq_large_simm(i32 %a) {
; CHECK-LABEL: cmpeq_large_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    setzi $m1, 1000
; CHECK-NEXT:    or $m1, $m1, 2147483648
; CHECK-NEXT:    cmpeq $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, -2147482648
  ret i1 %1
}

define i1 @cmpeq_large_simm_immz12(i32 %a) {
; CHECK-LABEL: cmpeq_large_simm_immz12:
; CHECK:         # %bb.0:
; CHECK-NEXT:    or $m1, $m15, 2147483648
; CHECK-NEXT:    cmpeq $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp eq i32 %a, -2147483648 ; bottom 20 bits are clear so no setzi required
  ret i1 %1
}

;===-----------------------------------------------------------------------===;
; icmp ne
;===-----------------------------------------------------------------------===;
define i1 @cmpne_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpne_reg:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpne $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ne i32 %a, %b
  ret i1 %1
}

define i1 @cmpne_zimm(i32 %a) {
; CHECK-LABEL: cmpne_zimm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, 42
; CHECK-NEXT:    cmpeq $m0, $m0, 0
; CHECK-NEXT:    br $m10
  %1 = icmp ne i32 %a, 42
  ret i1 %1
}

define i1 @cmpne_zero(i32 %a) {
; CHECK-LABEL: cmpne_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpne $m0, $m0, $m15
; CHECK-NEXT:    br $m10
  %1 = icmp ne i32 %a, 0
  ret i1 %1
}

define i1 @cmpne_large_zimm(i32 %a) {
; CHECK-LABEL: cmpne_large_zimm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    or $m1, $m15, 4293918720
; CHECK-NEXT:    cmpne $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ne i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpne_simm(i32 %a) {
; CHECK-LABEL: cmpne_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -1
; CHECK-NEXT:    cmpne $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ne i32 %a, -1
  ret i1 %1
}

define i1 @cmpne_large_simm(i32 %a) {
; CHECK-LABEL: cmpne_large_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -1
; CHECK-NEXT:    cmpne $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ne i32 %a, -1
  ret i1 %1
}

;===-----------------------------------------------------------------------===;
; icmp ugt
;===-----------------------------------------------------------------------===;
define i1 @cmpugt_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpugt_reg:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpult $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp ugt i32 %a, %b
  ret i1 %1
}

define i1 @cmpugt_zimm(i32 %a) {
; CHECK-LABEL: cmpugt_zimm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    setzi $m1, 42
; CHECK-NEXT:    cmpult $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp ugt i32 %a, 42
  ret i1 %1
}

define i1 @cmpugt_zero(i32 %a) {
; CHECK-LABEL: cmpugt_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpne $m0, $m0, $m15
; CHECK-NEXT:    br $m10
  %1 = icmp ugt i32 %a, 0
  ret i1 %1
}

define i1 @cmpugt_large_zimm(i32 %a) {
; CHECK-LABEL: cmpugt_large_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    or $m1, $m15, 4293918720
; CHECK-NEXT:    cmpult $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp ugt i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpugt_simm(i32 %a) {
; CHECK-LABEL: cmpugt_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    mov $m0, $m15
; CHECK-NEXT:    br $m10
  %1 = icmp ugt i32 %a, -1
  ret i1 %1
}

define i1 @cmpugt_large_simm(i32 %a) {
; CHECK-LABEL: cmpugt_large_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    mov $m0, $m15
; CHECK-NEXT:    br $m10
  %1 = icmp ugt i32 %a, -1
  ret i1 %1
}
;===-----------------------------------------------------------------------===;
; icmp uge
;===-----------------------------------------------------------------------===;
define i1 @cmpuge_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpuge_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpult $m0, $m0, $m1
; CHECK-NEXT:    cmpeq $m0, $m0, 0
; CHECK-NEXT:    br $m10
  %1 = icmp uge i32 %a, %b
  ret i1 %1
}

define i1 @cmpuge_zimm(i32 %a) {
; CHECK-LABEL: cmpuge_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m1, 41
; CHECK-NEXT:    cmpult $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp uge i32 %a, 42
  ret i1 %1
}

define i1 @cmpuge_zero(i32 %a) {
; CHECK-LABEL: cmpuge_zero:
; CHECK:         # %bb.0:
; CHECK-NEXT:    setzi $m0, 1
; CHECK-NEXT:    br $m10
  %1 = icmp uge i32 %a, 0
  ret i1 %1
}

define i1 @cmpuge_large_zimm(i32 %a) {
; CHECK-LABEL: cmpuge_large_zimm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    shr $m0, $m0, 20
; CHECK-NEXT:    setzi $m1, 4094
; CHECK-NEXT:    cmpult $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp uge i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpuge_simm(i32 %a) {
; CHECK-LABEL: cmpuge_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, -1
; CHECK-NEXT:    br $m10
  %1 = icmp uge i32 %a, -1
  ret i1 %1
}

define i1 @cmpuge_large_simm(i32 %a) {
; CHECK-LABEL: cmpuge_large_simm:
; CHECK:         # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, -1
; CHECK-NEXT:    br $m10
  %1 = icmp uge i32 %a, -1
  ret i1 %1
}
;===-----------------------------------------------------------------------===;
; icmp ult
;===-----------------------------------------------------------------------===;
define i1 @cmpult_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpult_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpult $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ult i32 %a, %b
  ret i1 %1
}

define i1 @cmpult_zimm(i32 %a) {
; CHECK-LABEL: cmpult_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpult $m0, $m0, 42
; CHECK-NEXT:    br $m10
  %1 = icmp ult i32 %a, 42
  ret i1 %1
}

define i1 @cmpult_zero(i32 %a) {
; CHECK-LABEL: cmpult_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    mov $m0, $m15
; CHECK-NEXT:    br $m10
  %1 = icmp ult i32 %a, 0
  ret i1 %1
}

define i1 @cmpult_large_zimm(i32 %a) {
; CHECK-LABEL: cmpult_large_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    shr $m0, $m0, 20
; CHECK-NEXT:    cmpult $m0, $m0, 4095
; CHECK-NEXT:    br $m10
  %1 = icmp ult i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpult_simm(i32 %a) {
; CHECK-LABEL: cmpult_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -1
; CHECK-NEXT:    cmpne $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ult i32 %a, -1
  ret i1 %1
}

define i1 @cmpult_large_simm(i32 %a) {
; CHECK-LABEL: cmpult_large_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -1
; CHECK-NEXT:    cmpne $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ult i32 %a, -1
  ret i1 %1
}
;===-----------------------------------------------------------------------===;
; icmp ule
;===-----------------------------------------------------------------------===;
define i1 @cmpule_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpule_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpult $m0, $m1, $m0
; CHECK-NEXT:    cmpeq $m0, $m0, 0
; CHECK-NEXT:    br $m10
  %1 = icmp ule i32 %a, %b
  ret i1 %1
}

define i1 @cmpule_zimm(i32 %a) {
; CHECK-LABEL: cmpule_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpult $m0, $m0, 43
; CHECK-NEXT:    br $m10
  %1 = icmp ule i32 %a, 42
  ret i1 %1
}

define i1 @cmpule_zero(i32 %a) {
; CHECK-LABEL: cmpule_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpeq $m0, $m0, 0
; CHECK-NEXT:    br $m10
  %1 = icmp ule i32 %a, 0
  ret i1 %1
}

define i1 @cmpule_large_zimm(i32 %a) {
; CHECK-LABEL: cmpule_large_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m1, 1
; CHECK-NEXT:    or $m1, $m1, 4293918720
; CHECK-NEXT:    cmpult $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp ule i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpule_simm(i32 %a) {
; CHECK-LABEL: cmpule_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m0, 1
; CHECK-NEXT:    br $m10
  %1 = icmp ule i32 %a, -1
  ret i1 %1
}

define i1 @cmpule_large_simm(i32 %a) {
; CHECK-LABEL: cmpule_large_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m0, 1
; CHECK-NEXT:    br $m10
  %1 = icmp ule i32 %a, -1
  ret i1 %1
}
;===-----------------------------------------------------------------------===;
; icmp sgt
;===-----------------------------------------------------------------------===;
define i1 @cmpsgt_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpsgt_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sgt i32 %a, %b
  ret i1 %1
}

define i1 @cmpsgt_zimm(i32 %a) {
; CHECK-LABEL: cmpsgt_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m1, 42
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sgt i32 %a, 42
  ret i1 %1
}

define i1 @cmpsgt_zero(i32 %a) {
; CHECK-LABEL: cmpsgt_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m15, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sgt i32 %a, 0
  ret i1 %1
}

define i1 @cmpsgt_large_zimm(i32 %a) {
; CHECK-LABEL: cmpsgt_large_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    or $m1, $m15, 4293918720
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sgt i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpsgt_simm(i32 %a) {
; CHECK-LABEL: cmpsgt_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -1
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sgt i32 %a, -1
  ret i1 %1
}

define i1 @cmpsgt_large_simm(i32 %a) {
; CHECK-LABEL: cmpsgt_large_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -1
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sgt i32 %a, -1
  ret i1 %1
}
;===-----------------------------------------------------------------------===;
; icmp sge
;===-----------------------------------------------------------------------===;
define i1 @cmpsge_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpsge_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m0, $m1
; CHECK-NEXT:    cmpeq $m0, $m0, 0
; CHECK-NEXT:    br $m10
  %1 = icmp sge i32 %a, %b
  ret i1 %1
}

define i1 @cmpsge_zimm(i32 %a) {
; CHECK-LABEL: cmpsge_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m1, 41
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sge i32 %a, 42
  ret i1 %1
}

define i1 @cmpsge_zero(i32 %a) {
; CHECK-LABEL: cmpsge_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m1, 41
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sge i32 %a, 42
  ret i1 %1
}

define i1 @cmpsge_large_zimm(i32 %a) {
; CHECK-LABEL: cmpsge_large_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m1, 1048575
; CHECK-NEXT:    or $m1, $m1, 4292870144
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sge i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpsge_simm(i32 %a) {
; CHECK-LABEL: cmpsge_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -2
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sge i32 %a, -1
  ret i1 %1
}

define i1 @cmpsge_large_simm(i32 %a) {
; CHECK-LABEL: cmpsge_large_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    add $m1, $m15, -2
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    br $m10
  %1 = icmp sge i32 %a, -1
  ret i1 %1
}
;===-----------------------------------------------------------------------===;
; icmp slt
;===-----------------------------------------------------------------------===;
define i1 @cmpslt_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpslt_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp slt i32 %a, %b
  ret i1 %1
}

define i1 @cmpslt_zimm(i32 %a) {
; CHECK-LABEL: cmpslt_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m0, 42
; CHECK-NEXT:    br $m10
  %1 = icmp slt i32 %a, 42
  ret i1 %1
}

define i1 @cmpslt_zero(i32 %a) {
; CHECK-LABEL: cmpslt_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    shr $m0, $m0, 31
; CHECK-NEXT:    br $m10
  %1 = icmp slt i32 %a, 0
  ret i1 %1
}

define i1 @cmpslt_large_zimm(i32 %a) {
; CHECK-LABEL: cmpslt_large_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    or $m1, $m15, 4293918720
; CHECK-NEXT:    cmpslt $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp slt i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpslt_simm(i32 %a) {
; CHECK-LABEL: cmpslt_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m0, -1
; CHECK-NEXT:    br $m10
  %1 = icmp slt i32 %a, -1
  ret i1 %1
}

define i1 @cmpslt_large_simm(i32 %a) {
; CHECK-LABEL: cmpslt_large_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m0, -1
; CHECK-NEXT:    br $m10
  %1 = icmp slt i32 %a, -1
  ret i1 %1
}
;===-----------------------------------------------------------------------===;
; icmp sle
;===-----------------------------------------------------------------------===;
define i1 @cmpsle_reg(i32 %a, i32 %b) {
; CHECK-LABEL: cmpsle_reg:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m1, $m0
; CHECK-NEXT:    cmpeq $m0, $m0, 0
; CHECK-NEXT:    br $m10
  %1 = icmp sle i32 %a, %b
  ret i1 %1
}

define i1 @cmpsle_zimm(i32 %a) {
; CHECK-LABEL: cmpsle_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m0, 43
; CHECK-NEXT:    br $m10
  %1 = icmp sle i32 %a, 42
  ret i1 %1
}

define i1 @cmpsle_zero(i32 %a) {
; CHECK-LABEL: cmpsle_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpslt $m0, $m0, 1
; CHECK-NEXT:    br $m10
  %1 = icmp sle i32 %a, 0
  ret i1 %1
}

define i1 @cmpsle_large_zimm(i32 %a) {
; CHECK-LABEL: cmpsle_large_zimm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    setzi $m1, 1
; CHECK-NEXT:    or $m1, $m1, 4293918720
; CHECK-NEXT:    cmpslt $m0, $m0, $m1
; CHECK-NEXT:    br $m10
  %1 = icmp sle i32 %a, 4293918720
  ret i1 %1
}

define i1 @cmpsle_simm(i32 %a) {
; CHECK-LABEL: cmpsle_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    shr $m0, $m0, 31
; CHECK-NEXT:    br $m10
  %1 = icmp sle i32 %a, -1
  ret i1 %1
}

define i1 @cmpsle_large_simm(i32 %a) {
; CHECK-LABEL: cmpsle_large_simm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    shr $m0, $m0, 31
; CHECK-NEXT:    br $m10
  %1 = icmp sle i32 %a, -1
  ret i1 %1
}